Symmetric clock receiver for differential input signals

A double data rate clock circuit, comprising:

• a first circuit stage including a differential amplifier for providing a first output signal and a second output signal, the first circuit stage including inputs for clock signals, the first circuit stage including a transfer gate for switching an output polarity by selecting one of the first output signal and the second output signal generated by the differential amplifier in accordance with a control signal;
• a second circuit stage coupled to the first circuit stage, the second circuit stage including a pulse generator for receiving the first output signal and the second output signal and generating clock pulses to be output from the pulse generator in accordance with the first output signal and the second output signal;
• and
• a toggle switch for generating the control signal based on an output of the pulse generator.

A clock circuit, comprising:

• a first circuit stage for providing a first output signal and a second output signal, the first circuit stage including inputs for clock signals;
• a switch coupled to the first stage for switching an output polarity by selecting one of the first output signal and the second output signal generated by the first circuit stage in accordance with a control signal;
• and
• a second circuit stage coupled to the first circuit stage through the switch, the second circuit stage for shaping the first output signal and the second output signal input thereto from the switch, the second circuit stage including an output for outputting clock pulses based on the first output signal and the second output signal, the control signal being generated from the clock pulses;
• a driver coupled to the switch, the driver including transfer gates driven by the output of the second stage, the driver for generating the control signal for the switch.