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US 6,294,936 B1Granted
Spread-spectrum modulation methods and circuit for clock generator phase-locked loop
AssigneeAmerican Microsystems, Inc.
InventorDaniel M. Clementi
Life of this patent
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AssigneeAmerican Microsystems, Inc.
InventorDaniel M. Clementi
Estimating the term…
A spread-spectrum modulation method and circuit for a clock generator phase-locked loop (PLL). A dither signal is injected into a PLL in synchronization with and having the same period or fraction of the same period as the phase comparison performed within the PLL. Over such period, the phase error caused by the modulation will integrate to zero and hence avoid transmitting a disturbance to the loop. A particular embodiment utilizes an output of the reference divider and/or feedback divider within the PLL to generate the dither signal. Such a configuration avoids the need for additional hardware which otherwise would increase the chip area and/or cost of the device. The reference divider and/or feedback divider is made up preferably of a linear feedback shift register (LFSR). One or more stages of the LFSR provide an output which is used to generate the dither signal. In a preferred embodiment, the output from the LFSR exhibits a pseudo-random sequence.
A clock generator phase-locked loop, comprising:
A clock generator phase-locked loop, comprising:
A method for dithering a clock generator phase-locked loop including a reference frequency source for providing a reference frequency, a phase comparator for producing a control signal based on a periodic comparison of a phase difference between respective signals provided to a first input and a second input of the phase comparator, the reference frequency being operatively coupled to the first input, a voltage-controlled oscillator for generating an output frequency based on the control signal provided by the phase comparator, and a feedback divider which receives and divides the output frequency to provide a divider output which is operatively coupled to the second input of the phase comparator, the method comprising the step of:
A method for dithering a clock generator phase-locked loop including a reference frequency source for proving a reference frequency, a phase comparator for producing a control signal based on a phase difference between respective signals provided to a first input and a second input of the phase comparator, the reference frequency being operatively coupled to the first input, a voltage-controlled oscillator for generating an output frequency based on the control signal provided by the phase comparator, and a feedback divider which receives and divides the output frequency to provide a divider output which is operatively coupled to the second input of the phase comparator, wherein at least one of a reference divider included in the reference frequency source and the feedback divider comprises a linear feedback shift register counter having a plurality of stages, the method comprising the step of:
Dependencies are inferred from the claim text.