Built-in-self-test circuitry for testing a phase locked loop circuit
AssigneeVLSI Technology, Inc.
InventorRussell George Ott
Life of this patent
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AssigneeVLSI Technology, Inc.
InventorRussell George Ott
Estimating the term…
A built-in-self-test circuit aids in testing a phase locked loop circuit. The phased locked loop has a plurality of frequency multipliers. The built-in-self-test circuit includes a frequency divider and a multiplexer. The frequency divider has a plurality of divide-by-counters. For each frequency multiplier within the plurality of frequency multipliers there is a corresponding divide-by-counter. A ratio of a multiplier for each frequency multiplier to a divider of its corresponding divide-by-counter is a constant for all frequency multipliers and corresponding divide-by-counters. When a frequency multiplier within the plurality of frequency multipliers is selected, the multiplexer selects its corresponding divide-by-counter to produce a test output clock.
A built-in-self-test circuit for aid in testing a phase locked loop circuit having a plurality of frequency multipliers, the built-in-self-test circuit comprising:
A method for testing a phase locked loop circuit having a plurality of frequency multipliers, the method comprising the following steps:
A circuit comprising:
Dependencies are inferred from the claim text.