A digital position sensor according to claim 1, for providing the position of a rotating component with a resolution equal to 29, wherein the generation means (1) for generation of the signals (Si) of the processing device generates 2m−1=8 signals (S1 to S8), phase shifted by 45E with respect to one another, having the values:
- S 7 = - S 1 S 5 = - S 2 S 3 = S 1 + S 2 2 S 6 - = - S 3 S 4 = S 1 - S 2 2 S 8 = - S 4 which are obtained from summing circuits (7), NOT circuits (8) and amplifiers (9). 7. A digital position sensor according to claim 6, wherein the detection means (2) for detection of the 2m=16 sectors (Pi) includes four combinations (C6 to C9) of comparators (10) and of logic gates (11) of the AND and OR type, delivering the following digital signals:
- b9=1 if S70, b8=1 if S50, B7=1 if (S30 and S40) or (S60 and S80), b6=1 if (S1S8 and S2S4) or (S5S3 and S1S6) or (S7S4 and S5S8) or (S2S6 and S7S3). 8. A digital position sensor according to claim 1, wherein the processing device further comprises:
- generation means (7) for generating a digital output signal (bQUAD) I in quadrature with the digital output signal (b1) corresponding to the lowest order bit of the output signal of the digital position sensor and with the same resolution;
- generation means (8) for generating a reference pulse (bTT), where said digital signals (b1), (bQUAD) and (bTT) give the relative position of the rotating component. 9. A digital position sensor according to claim 8, wherein the generation means (7) for generating a digital output signal (bQUAD) performs the following Boolean operation by means of the Exclusive-OR (XOR) logical operator:
- bQUAD=b2 or b3 or . . . or bn−1 or bn. 10. A digital position sensor according to claim 8, wherein the generation means (8) for generating a reference pulse (bTT) performs the following Boolean operation:
- bTT=b1 and b2 and . . . and bn−1 and bn. 11. A digital position sensor according to claim 9, wherein the generation means (7) for generating a digital output signal (bQUAD) consists of an Exclusive-OR logic circuit receiving as input the digital output signals (b2 to bn), with the exception of the signal (b1) corresponding to the lowest order bit of the output signal of the digital position sensor, and by the fact that the means (8) for generating a reference pulse (bTT) consists of several AND and NOT logic gates. 12. A digital position sensor according to claim 10, wherein the generation means (7) for generating a digital output signal (bQUAD) consists of an Exclusive-OR logic circuit receiving as input the digital output signals (b2 to bn), with the exception of the signal (b1) corresponding to the lowest order bit of the output signal of the digital position sensor, and by the fact that the means (8) for generating a reference pulse (bTT) consists of several AND and NOT logic gates. 13. A digital position sensor according to claim 5, wherein the interpolation means (4) includes resistive networks attenuating the signal (B). 14. A digital position sensor according to claim 1, wherein the n digital output signals (bi) are serialized by means of a data transmission protocol integrated in the processing device. 15. A digital position sensor according to claim 1, wherein the coding of the n digital output signals (b1 to bn) makes it possible to define unambiguously the absolute position of the sensor. 16. A digital position sensor according to claim 2, wherein the multiplexing means (3) generates the signals (A and B) from thresholds (L1) and (L2) of determined values:
- L1=A0 sin(2π/2m) L2=A0 sin(2π/2m−1). 17. A digital position sensor according to claim 16, wherein the multiplexing means (3) includes 2m combinations of logic circuits, such as NOT and AND gates. 18. A digital position sensor according to claim 2, wherein the interpolation means (4) generates signals (Bj), where j is a whole number varying from 1 to (2n−m−1), which are attenuations of the signal (B) by attenuation factors (kj), with values equal to:
- Kj=−sin(j*2π/2n)/sin(j*2π/2n−2π/2m−1) compares each signal (Bj) with the signal (A), then executes logical combinations of the digital signals coming from these comparisons, in order to deliver the (n−n) digital output signals (b1, b2, . . . bn−m−1, bn−m) corresponding to the low order bits of the signal. 19. A digital position sensor according to claim 2, for providing the position of a rotating component with a resolution equal to 29, wherein the generation means (1) for generation of the signals (Si) of the processing device generates 2m−1=8 signals (S1 to S8), phase shifted by 45E with respect to one another, having the values:
- S 7 = - S 1 S 5 = - S 2 S 3 = S 1 + S 2 2 S 6 - = - S 3 S 4 = S 1 - S 2 2 S 8 = - S 4 which are obtained from summing circuits (7), NOT circuits (8) amplifiers (9). 20. A digital position sensor according to claim 19, wherein the detection means (2) for detection of the 2m=16 sectors (Pi) includes four combinations (C6 to C9) of comparators (10) and of logic gates (11) of the AND and OR type, delivering the following digital signals:
- b9=1 if S70, b8=1 if S50, B7=1 if (S30 and S40) or (S60 and S80), b6=1 if (S1S8 and S2S4) or (S5S3 and S1S6) or (S7S4 and S5S8) or (S2S6 and S7S3). 21. A digital position sensor according to claim 18, wherein the interpolation means (4) includes resistive networks attenuating the signal (B). 22. A digital position sensor according to claim 2, wherein the n digital output signals (bi) are serialized by means of a data transmission protocol integrated in the processing device. 23. A digital position sensor according to claim 2, wherein the coding of the n digital output signals (b1 to bn) makes it possible to define unambiguously the absolute position of the sensor.