Dual-thickness solder mask in integrated circuit package
AssigneeLSI Logic Corporation
InventorJohn P. McCormick
Life of this patent
Estimating the term…
Abstract
Provided is a two-step, dual-thickness solder mask material on the substrate surface. The material is preferably applied in a series of screenings: A first screening of the solder mask material in the region where the chip will be placed, and a second screening of solder mask surrounding the place on the substrate surface where the die will be placed, normally over the outside edge regions of the substrate surface. The thickness of this first screening of solder mask may be from about 10 to 20 microns, while the thickness of the second screening of solder mask is about conventional thickness for a solder mask, for example from about 30 to 40 microns.
Claims9
A semiconductor package, comprising:
- a packaging substrate having a chip-connecting surface;
- an integrated circuit chip electrically and mechanically bound to said substrate in a chip bonding area on said chip-connecting surface;
- a plurality of regions of solder mask on said chip-connecting surface, said plurality of regions comprising,
- a first region between said chip and said chip-connecting surface in the chip bonding area of said substrate and having a first thickness, and
- a second region outside said chip bonding area of said chip, and having a second thickness greater than said first thickness.
Dependencies are inferred from the claim text.