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AssigneeInternational Business Machines Corporation
InventorsHormazdyar M. Dalal, Du Binh Nguyen, Hazara S. Rathore
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The present invention relates generally to a new sequence of methods and materials to improve the process yield and to enhance the reliability of multilevel interconnection with sub-half-micron geometry by making judicious use of composite insulators to prevent metal thinning over hard metal via plugs and by preventing process induced metal spike formation. The method takes advantage of the double damascene process. The metal spikes and the metal thinning resulting from over etch process is prevented in this method by using a pair of insulators which require different chemistries for etching.
A semiconductor substrate having at least one high electrical conductivity interconnect, wherein said substrate comprising at least one p/n junction in electrical contact with a metallic via-plug, at least one first insulator layer over said semiconductor substrate and surrounding said first metallic via-plug, at least a portion of at least one first level of high electrical conductivity interconnection line in contact with said first metallic via-plug, wherein a second and a third insulator layers are over said first insulator layer and surrounds said first level electrical interconnection line, at least a portion of at least one second level electrical interconnection line in contact with said first level electrical interconnection line through at least one high electrical conductivity via-plug, wherein at least a fourth and a fifth insulator layers are over said third insulator layer and surrounds said second level electrical interconnection line, and wherein each adjoining insulator layer is of a different material, and thereby forming said semiconductor substrate having at least one high electrical conductivity interconnect.
Dependencies are inferred from the claim text.