US 6,294,813 B1Granted

Information handling system having improved floating gate tunneling devices

AssigneeMicron Technology, Inc.

InventorsLeonard Forbes, Joseph E. Geusic

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Abstract

A method and structure for textured surfaces in non volatile floating gate tunneling oxide (FLOTOX) devices, e.g. FLOTOX transistors, are provided. The present invention capitalizes on using “self-structured masks” and a controlled etch to form nanometer scale microtip arrays to form the textured surfaces. The present invention further employs atomic layer epitaxy (ALE) to create a very conformal tunnel oxide layer which complements the nanometer scale microtip arrays. The resulting structure provides a higher tunneling current than currently exists in FLOTOX technology. The improved tunneling currents at low voltages can make these FLOTOX devices suitable for replacing DRAMS.

Claims17

Dependent claims

A information handling system, comprising:

a memory array, wherein the memory array comprises:
a number of floating gate tunneling oxide (FLOTOX) transistors, wherein each FLOTOX comprises:
a substrate, the substrate having a first source/drain region, a second source/drain region, and a body region, the substrate having a textured surface, the textured surface including an array of microtips, each microtip having a top surface, and wherein the microtips have an average density of 1012/cm2;
a tunnel oxide layer formed on the textured surface of the substrate, wherein the tunnel oxide layer is deposited using atomic layer epitaxy (ALE);
a first conductive layer formed on the tunnel dielectric;
an insulator layer formed on the first conductive layer;
and
a second conductive layer formed on the insulator layer;
a number of wordlines, wherein each wordline couples the second conductive layer for a number of FLOTOX transistors;
a number of bitlines, wherein each bitline couples the second source/drain region for a number of FLOTOX transistors;
a number of sense amplifiers, wherein each sense amplifier couples to select number of the number of bitlines;
and
a number of sourcelines, wherein each sourceline couples a first source/drain region for a number of FLOTOX transistors;
a central processing unit;
and
a system bus, wherein the system bus couples the memory array to the central processing unit.

13 more elements

A information handling system, comprising:

a memory array, wherein the memory array comprises:
a number of floating gate tunneling oxide (FLOTOX) transistors, wherein each FLOTOX comprises:
a first interface having a first and second source/drain region and a body region therebetween on a first portion of the first interface, wherein the first portion includes a surface having an array of asperities, each asperity having a top surface, the asperities in the array of asperities having an average density of 1012/cm2, the first interface having a first dielectric as a second portion of the first interface;
a first dielectric/polysilicon interface adjacent to the first interface;
a polysilicon/second dielectric interface adjacent to the first dielectric/polysilicon interface;
and
a second dielectric/polysilicon interface adjacent to the polysilicon/second dielectric interface;
a number of wordlines, wherein each wordline couples the second dielectric/polysilicon interface for a number of FLOTOX transistors;
a number of bitlines, wherein each bitline couples the second source/drain region for a number of FLOTOX transistors;
a number of sense amplifiers, wherein each sense amplifier couples to a select number of the number of bitlines;
and
a number of sourcelines, wherein each sourceline couples the first source/drain region for a number of FLOTOX transistors;
a central processing unit;
and
a system bus, wherein the system bus couples the memory array to the central processing unit.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/504,496Filed 15 Feb 2000 · division
Priority: 29 May 1998
Granted: 25 Sep 2001
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10D 64/01342
On single crystalline silicon, e.g. chemical oxidation using a liquid: by deposition, e.g. evaporation, ALD or laser deposition
H10D 30/683
Having only two programming levels: programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
H10D 64/035
Of data-storage electrodes: comprising conductor-insulator-conductor-insulator-semiconductor structures
H10D 64/68
Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes: characterised by the insulator, e.g.…

Family

Application09/087,473Parent of this division · filed 29 May 1998
US 6,025,627 AParent of this division
US 6,294,813 B1This patent

From the US filing history. Foreign family members aren’t listed.

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