Method for making integrated circuits having features with reduced critical dimensions

A method for making an integrated circuit comprising the steps of:

• forming a metal layer adjacent a semiconductor wafer;
• forming a positive photoresist layer adjacent the metal layer, with at least a portion of the metal layer being uncovered;
• exposing the photoresist layer to a pattern image;
• developing the exposed photoresist layer using a developer and stripping away undeveloped photoresist portions to define a mask including mask features having reduced widths than would otherwise be produced adjacent the metal layer and based upon an interaction between the photoresist, the developer and the metal;
• and
• etching the metal layer using the mask including mask features having the reduced widths to thereby define circuit features having a smaller critical dimension than would otherwise be produced.

A method for making an integrated circuit comprising the steps of:

• forming a dielectric layer adjacent a semiconductor wafer;
• forming an aluminum layer adjacent the dielectric layer;
• forming a photoresist layer adjacent the aluminum layer with at least a portion of the aluminum layer being uncovered;
• exposing the photoresist layer to a pattern image;
• developing the exposed photoresist layer using a developer and stripping away undeveloped photoresist portions to define a mask including mask features having reduced widths than would otherwise be produced adjacent the aluminum layer and based upon an interaction between the photoresist, the developer and the aluminum;
• and
• etching the aluminum layer using the mask including features having the reduced widths to thereby define circuit features having a smaller critical dimension than would otherwise be produced.