Method for the formation of a polysilicon layer with a controlled, small silicon grain size during semiconductor device fabrication

A polysilicon layer forming method for formation of a polysilicon layer with controlled silicon grain size during a semiconductor device fabrication operation including semiconductor device fabrication steps, the polysilicon layer forming method comprising the steps of:

• (a) providing a semiconductor substrate;
• (b) forming a silicon dioxide layer on the surface of the semiconductor substrate;
• (c) depositing an amorphous silicon layer on the silicon dioxide layer;
• (d) forming a plurality of silicon crystallites in the amorphous silicon layer by subjecting the amorphous silicon layer to a first thermal cycle;
• and
• (e) after forming the silicon crystallites, performing one of the semiconductor device fabrication steps in a manner subjecting the amorphous silicon layer and the silicon crystallites to at least one additional thermal cycle, thereby growing the silicon crystallites into silicon grains having silicon grain size not greater than 50 nm and forming a polysilicon layer with controlled silicon grain size not greater than 50 nm, wherein said one of the semiconductor device fabrication steps performed during step (e) is a step associated with the formation of silicon dioxide/silicon nitride sidewall spacers during the semiconductor device fabrication.

A polysilicon layer forming method for the formation of a polysilicon layer with a controlled silicon grain size during a semiconductor device fabrication operation including semiconductor device fabrication steps, the polysilicon layer forming method comprising the steps of:

• (a) providing a semiconductor substrate;
• (b) forming a gate silicon dioxide layer on the surface of the semiconductor substrate;
• (c) depositing an amorphous silicon layer on the gate silicon dioxide layer using a low pressure chemical vapor deposition technique at a temperature in the range of 520° C. to 560° C. and a pressure in the range of 150 mTorr to 250 mTorr, the amorphous silicon layer having a thickness in the range of 1000 angstroms to 2500 angstroms;
• (d) forming a plurality of silicon crystallites in the amorphous silicon layer by subjecting the amorphous silicon layer to a first thermal cycle that includes a temperature ramp rate of at least 50° C. per second and an annealing step at a temperature in the range of 740° C. to 760° C. for a time period of 30 seconds to 90 seconds;
• (e) patterning the amorphous silicon layer with the silicon crystallites therein to form a patterned amorphous silicon layer with said silicon crystallites therein, the patterned amorphous silicon layer including silicon gate electrodes with a width in the range of 0.10 μm to 0.25 μm ;
• and
• (f) after step (e), performing one of the semiconductor device fabrication steps in such a manner as to subject the patterned amorphous silicon layer with said silicon crystallites to at least one additional thermal cycle, thereby converting said patterned amorphous silicon layer with said silicon crystallites into a patterned polysilicon layer with silicon grains of controlled size, wherein said silicon grains have grain size not greater than 50 nm.