Gate re-masking for deeper source/drain co-implantation processes

A method, comprising:

• forming a gate stack comprised of a gate electrode above a semiconducting substrate, said gate stack having a plurality of sidewalls;
• performing a first ion implantation process to form a first doped region in said substrate;
• forming at least one sidewall spacer adjacent said sidewalls of said gate stack;
• performing a second ion implantation process in said substrate;
• forming a masking layer above at least said gate electrode after said second ion implantation process is performed;
• performing a third ion implantation process after said masking layer is formed to form a third doped region in said substrate;
• and
• annealing said first, second and third doped regions.

A method, comprising:

• forming a gate stack comprised of a gate electrode above a semiconducting substrate, said gate stack having a plurality of sidewalls;
• performing a first ion implantation process at a dopant concentration ranging from approximately 1×1014-1×1015 ions/cm2 and at an energy level ranging from approximately 3-5 keV to form a first doped region in said substrate;
• forming at least one sidewall spacer adjacent said sidewalls of said gate stack;
• performing a second ion implantation process at a dopant concentration ranging from approximately 1-5×1015 ions/cm2 and at an energy level ranging from approximately 5-30 keV in said substrate;
• forming a masking layer above at least said gate electrode after said second ion implantation process is performed;
• performing a third ion implantation process after said masking layer is formed at a dopant concentration ranging from approximately 1×1013-1×1014 ions/cm2 and at an energy level ranging from approximately 60-300 keV to form a third doped region in said substrate;
• and
• annealing said first, second and third doped regions.