Super halo implant combined with offset spacer process
AssigneeUnited Microelectronics Corp.
InventorsTony Lin, Jih-Wen Chou
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Abstract
A method for forming a semiconductor structure by using super halo implant combined with offset spacer process is disclosed. This invention comprises providing a substrate with a gate electrode formed thereon and a halo implant region formed therein. Then, a dielectric layer is deposited on the substrate and the gate electrode. Next, the semiconductor structure is annealed, and the dielectric layer is anisotropically etched to form an offset spacer.
Claims15
A method for forming a semiconductor device by using halo implant combined with offset spacer process, wherein said semiconductor device is formed on a wafer, said method comprising:
- providing a substrate having a gate electrode formed thereon and a halo implant region formed therein;
- depositing a dielectric layer on said substrate and said gate electrode;
- annealing said wafer;
- anisotropically etching said dielectric layer to form an offset spacer;
- implanting ions into said substrate to form source/drain extension regions;
- forming a spacer on the sidewall of said gate;
- and
- implanting ions into said substrate to form source/drain regions.
A method for forming a semiconductor device, said method comprising:
- providing a semiconductor structure having a semiconductor substrate, wherein a gate electrode is formed on the substrate;
- forming a halo implant region in said substrate under said gate electrode;
- depositing a dielectric layer on said semiconductor structure;
- annealing said semiconductor structure;
- anisotropically etching said dielectric layer to form an offset spacer;
- implanting ions into said substrate to form source/drain extension regions;
- forming a spacer on the sidewall of said gate;
- and
- implanting ions into said substrate to form source/drain regions.
A method for forming a metal-oxide-semiconductor transistor having a channel of a predetermined channel conductivity type, said channel defining a channel region, said metal-oxide-semiconductor transistor having a source and a drain of a source conductivity type opposite said channel conductivity type, said source defining a source region, said drain defining a drain region, said method comprising:
- providing a substrate;
- forming a gate electrode on said substrate;
- implanting a halo dopant of said channel conductivity type to a halo implant region in said substrate under said channel;
- depositing a dielectric layer on said substrate and said gate electrode;
- annealing said substrate;
- anisotropically etching said dielectric layer to form offset spacer;
- forming source/drain extension regions;
- forming a spacer on the sidewall of said offset spacer beside said gate electrode;
- and
- forming source/drain regions in said substrate.
Dependencies are inferred from the claim text.