A method of fabricating a capacitor under bit line (CUB), structure for a DRAM device, on a semiconductor substrate, featuring the selective truncation of polysilicon plug structures exposed in capacitor openings, allowing increased capacitance to be achieved via accommodation of larger vertical dimensioned capacitor structures, and without increasing the aspect ratio of a dry etched, narrow diameter, bit line contact hole, comprising the steps of:
- forming transfer gate transistors on said semiconductor substrate, comprised of insulator capped gate structures on an underlying silicon dioxide gate insulator layer, with source/drain regions located in a region of said semiconductor substrate not covered by said insulator capped gate structures;
- depositing a silicon nitride layer;
- depositing a first silicon oxide layer;
- planarizing said first silicon oxide layer;
- forming self-aligned contact (SAC), openings in said first silicon oxide, and in said silicon nitride layer, resulting in silicon nitride spacers on the sides of said insulator capped gate structures, and with said SAC opening exposing a portion of the top surface of said source/drain region;
- depositing a first polysilicon layer completely filling said SAC openings;
- removing portions of said first polysilicon layer from the top surface of said first silicon oxide layer forming said polysilicon plug structures in said SAC openings;
- depositing a second silicon oxide layer;
- depositing a thin silicon nitride stop layer;
- forming said capacitor openings in said thin silicon nitride stop layer, in said second silicon oxide layer, and in a top portion of said first silicon oxide layer, exposing top portions of a first group of polysilicon plug structures, while the bottom portions of said polysilicon plug structures remain embedded between insulator capped gate structures, and while a second polysilicon plug structure remains covered by overlying thin silicon nitride stop layer and by said second silicon oxide layer;
- selectively removing said top portions of said first group of polysilicon plug structures exposed in said capacitor opening, to create truncated polysilicon plug structures in said capacitor openings, shorter in length than said second polysilicon plug structure;
- forming storage node structures in said capacitor openings, with each storage node structure comprised of hemispherical grain (HSG), silicon layer, on an underlying amorphous silicon layers, with said thin silicon nitride stop layer removed during definition of said storage node structures;
- depositing a capacitor dielectric layer;
- depositing a second polysilicon layer, completely filling said capacitor openings;
- patterning of said second polysilicon layer to form top electrode structure of said capacitor structure, in said capacitor opening, with said capacitor structure overlying and contacting said truncated polysilicon plug structures, and with each capacitor structure comprised of a top electrode structure, comprised with said capacitor dielectric layer, and comprised with said storage node structure;
- depositing a third silicon oxide layer;
- performing a dry etch procedure to create said narrow diameter, bit line contact hole in said third silicon oxide layer, and in said second silicon oxide layer, exposing a portion of said second polysilicon plug structure, embedded in said first silicon oxide layer;
- depositing a titanium nitride-tungsten layer, completely filling said narrow diameter, bit line contact hole;
- and
- patterning of said titanium nitride-tungsten layer, to form a bit line structure in said narrow diameter, bit line contact hole.