Methods of forming integrated circuit capacitors by electroplating electrodes from seed layers

The method of forming an integrated circuit memory device capacitor, comprising the steps of:

• forming an electrode pad on an integrated circuit substrate;
• forming a first interlevel dielectric layer on the electrode pad;
• forming a plurality of bit lines on the first interlevel dielectric layer;
• forming a seed layer on the plurality of bit lines;
• forming a plating mask layer on the seed layer;
• selectively etching the plating mask layer and the seed layer to define an opening therein that exposes sidewalls of the seed layer;
• and
• electroplating at least a portion of a first capacitor electrode into the opening, using the exposed sidewalls of the seed layer as an electroplating seed.

A method for manufacturing a capacitor of a semiconductor memory device, comprising the steps of:

• (a) forming a lower electrode seed layer over a semiconductor substrate having a conductive region electrically connected to an active region formed in the semiconductor substrate;
• (b) forming a plating mask layer over the lower electrode seed layer;
• (c) patterning the plating mask layer and the lower electrode seed layer to form a plating mask pattern and a lower electrode seed pattern, both of which define a region where a capacitor lower electrode is to be formed, thereby forming an opening exposing the conductive region and the sidewalls of the plating mask pattern;
• (d) performing electroplating using the lower electrode seed pattern exposing its sidewalls by the opening, to form a lower electrode conductive layer in the opening;
• and
• (e) removing the plating mask pattern and the lower electrode seed pattern to expose the sidewalls of the lower electrode conductive layer, thereby resulting in a capacitor lower electrode.

A method for manufacturing a capacitor of a semiconductor memory device, comprising the steps of:

• (a) forming a lower electrode pad with a conductive material on an active region of a semiconductor substrate;
• (b) forming a first interlevel dielectric (ILD) film over the lower electrode pad;
• (c) forming bit lines on the first ILD film;
• (d) forming a second ILD film over the bit lines;
• (e) forming a lower electrode seed layer over the second ILD film;
• (f) forming a plating mask layer over the lower electrode seed layer;
• (g) patterning the plating mask layer, the lower electrode seed layer, the second ILD film and the first ILD film by photolithography to form an opening exposing the lower electrode pad;
• (h) filling the opening with a conductive layer, the conductive layer deposited on or over the substantially the same level to the top of the lower electrode seed layer, by electroplating with the patterned lower electrode seed layer;
• and
• (i) removing the patterned plating mask and lower electrode seed layer to expose the sidewalls of the conductive layer, thereby forming a capacitor lower electrode.