US 6,294,419 B1 · Structure and method for improved latch-up using dual depth STI with impurity implant

Abstract

A method and structure for improving the latch-up characteristic of semiconductor devices is provided. A dual depth STI is used to isolate the wells from each other. The trench has a first substantially horizontal surface at a first depth and a second substantially horizontal surface at a second depth which is deeper than the first depth. The n- and p-wells are formed on either side of the trench. A highly doped region is formed in the substrate underneath the second substantially horizontal surface of the trench. The highly doped region abuts both the first and the second wells and extends the isolation of the trench.

Claims17

Dependent claims

A method for making a dual depth trench, the method comprising:

a) providing a substrate having at least one dielectric layer thereon and a resist layer on said dielectric layer;
b) patterning said resist layer and forming a trench through said at least one dielectric layer into said substrate according to said patterned resist layer;
c) implanting a dopant into said substrate using said patterned resist layer as a mask for forming a doped region in said substrate below said trench;
d) removing said resist and said at least one dielectric layer adjacent said trench;
e) etching said substrate exposed by step d) simultaneously with said trench until a bottom of said trench reaches said doped region for forming a dual depth trench;
f) filling said dual depth trench;
and
g) implanting wells of opposite conductivity types into said substrate on opposite sides of said dual depth trench.

5 more elements

A method of forming a semiconductor device comprising:

a) providing a substrate;
b) depositing a hybrid resist on said substrate;
c) exposing said hybrid resist through a mask containing a plurality of shapes, wherein portions of said hybrid resist blocked by said mask shapes are unexposed, portions of said hybrid resist not blocked by said mask are fully exposed and transition areas of said hybrid resist under mask shape edges are exposed with an intermediate exposure;
d) developing said hybrid resist such that portions of said hybrid resist which were exposed to intermediate amounts of exposure are removed thereby forming a plurality of well edge spaces;
e) etching said substrate according to said patterned hybrid resist to form a first trench;
f) implanting a dopant into said substrate below said first trench using said patterned hybrid resist as a mask;
g) removing said hybrid resist adjacent said first trench;
h) etching said substrate exposed by step g) simultaneously with said first trench until a bottom of said first trench reaches said doped region for forming a dual depth trench;
i) filling said dual depth trench;
and
j) implanting wells of opposite conductivity types into said substrate on opposite sides of said dual depth trench.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application

09/705,882Filed 6 Nov 2000 · division

Priority

30 Apr 1999

Granted

25 Sep 2001

Term ends

Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10W 10/17
Isolation regions comprising dielectric materials: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
H10D 84/0188
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their isolation regions
H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10W 10/0145
Using trench refilling with dielectric materials, e.g. shallow trench isolations: of trenches having shapes other than rectangular or V-shape

Structure and method for improved latch-up using dual depth STI with impurity implant

Life of this patent

Structure and method for improved latch-up using dual depth STI with impurity implant

Life of this patent

Abstract

Claims17