Semiconductor integrated circuit having function of reducing a power consumption and semiconductor integrated circuit system comprising this semiconductor integrated circuit

A semiconductor integrated circuit system comprising:

• a static semiconductor memory device selected in response to a chip selection signal for operating in synchronization with a clock signal;
• a backup circuit supplying backup power to said static semiconductor memory device following step-down of a power supply voltage supplied to said static semiconductor memory device;
• a stabilizing circuit for stepping down said power supply voltage when said power supply voltage is stepped up beyond a prescribed value;
• a backup controller sensing abrupt step-down of said power supply voltage and switching said chip selection signal to a nonselective state;
• and
• a controller for switching said static semiconductor memory device to a power down mode/operating mode.

A semiconductor integrated circuit comprising:

• a generation circuit generating a first internal clock synchronous with an external clock and a second internal clock obtained by delaying said first internal clock;
• a memory cell array including memory cells arranged in rows and columns, a plurality of word lines corresponding to said rows and a plurality of pairs of bit lines corresponding to said columns;
• and
• a word line activation signal generation circuit activating a word line activation signal supplied to selected said word line, wherein
• said word line activation signal generation circuit decides an active period of said word line activation signal in response to edges of said first internal clock and said second internal clock.