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US 6,292,061 B1Granted
Low-voltage CMOS phase-locked loop (PLL) for high-performance microprocessor clock generation
AssigneeSandCraft, Inc.
InventorMing Qu
Life of this patent
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Abstract
A PLL is implemented as a full differential circuit to improve the jitter performance and the operating voltage range. A process-compensated common-mode feedback is designed in the differential charge pump which together with loop filter of MOSFET capacitors maximizes the dynamic voltage range. A high-frequency divider capable of divide-mode change-on-flight is developed with eight divide mode programmability. A PLL start-up control circuit makes the PLL start and work under difficult conditions.
Claims4
A phase-locked loop (PLL) with a supply voltage Vdd, said PLL comprising:
- a voltage controlled oscillator (VCO);
- a loop filter coupled to said VCO, said loop filter having a plurality of MOSFET gate capacitors with a process dependent thresh-hold voltage of approximately Vth, said loop filter having a first filter terminal with a first filter terminal voltage of Vf1 and a second filter terminal with a second filter terminal voltage of Vf2;
- a differential charge pump (CP) coupled to said loop filter, wherein said differential CP is adapted to sense said thresh-hold voltage Vth and maintain at a node a common-mode reference voltage of Vref approximately equal to (Vdd−Vth)/2, and wherein said differential CP has a common-mode feedback for centering Vf1 and Vf2 around Vref.
Dependencies are inferred from the claim text.