Internal clock signal generating circuit having function of generating internal clock signals which are multiplication of an external clock signal

An internal clock signal generating circuit, comprising:

• first clock signal generating means for generating, based on an external clock signal, a first internal clock signal synchronized in phase with said external clock signal;
• and
• second clock signal generating means for generating, based on the first internal clock signal output from said first clock signal generating means, a second internal clock signal synchronized in phase with said first internal clock signal;
• said first clock signal generating means including
• a first delay line for delaying an input signal and outputting said fist internal clock signal,
• selecting means for selectively outputting to said first delay line one of the first internal clock signal output from said first delay line and said external clock signal,
• frequency dividing means for frequency-dividing said first internal clock signal, and
• first delay control means for detecting a phase difference between a signal output from said frequency-dividing means and said external clock signal, and for controlling the delay time of said first delay line based on a result of the detection;
• and
• said second clock signal generating means including
• a second delay line for delaying said first internal clock signal and outputting said second internal clock signal, and
• second delay control means for detecting a phase difference between the second internal clock signal output from said second delay line and said first internal clock signal, and for controlling the delay time of said second delay line based on a result of the detection.

An internal clock signal generating circuit, comprising:

• first clock signal generating means for generating, based on an external clock signal, a first internal clock signal synchronized in phase with said external clock signal;
• and
• second clock signal generating means for generating, based on the first internal clock signal output from said first clock signal generating means, a second internal clock signal synchronized in phase with said external clock signal;
• wherein said first clock signal generating means includes
• a first delay line for delaying an input signal and outputting said first internal clock signal,
• selecting means for selectively outputting to said first delay line one of the first internal clock signal output from said first delay line and said external clock signal,
• first frequency dividing means for frequency-dividing said first internal clock signal, and
• first delay control means for detecting a phase difference between a signal output from said first frequency dividing means and said external clock signal and for controlling the delay time of said first delay line based on a result of the detection;
• and
• said second clock signal generating means includes
• a second delay line for delaying said first internal clock signal and outputting said second internal clock signal,
• second frequency dividing means for frequency dividing said second internal clock signal, and
• second delay control means for detecting a phase difference between a signal output from said second frequency dividing means and said external clock signal and controlling the delay time of said second delay line based on a result of the detection.