Flash memory architecture and method of operation
AssigneeAzalea Microelectronics Corporation
InventorsEungjoon Park, Ali Pourkeramati
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Abstract
A flash memory device and its method of operation provide for selective, e.g., bit-by-bit, erase operation resulting in much narrower distribution for erase threshold voltage VTE. Latches that couple to the array are set or reset depending on cell content during erase verify. The output of the latches are then applied to selected cells to perform erase. The flash architecture allows for bit-by-bit erase verify operation resulting in a tighter VTE distribution and elimination of the need for preprogramming. In a preferred embodiment, the flash cell is programmed by CHE tunneling and erased by FN tunneling both occurring on the same side (e.g., drain side) of the cell transistor.
Claims20
A flash memory device comprising:
- a plurality of memory cells arranged in a two-dimensional array of rows and columns;
- a plurality of latches respectively coupled to the plurality of columns of memory cells;
- a first decoder coupled to the plurality of columns;
- a sense amplifier having an input coupled to the first decoder and an output;
- and
- a second decoder having an input coupled to the output of the sense amplifier and a plurality of outputs respectively coupled to a plurality of set/reset inputs of the plurality of latches,
- wherein, each of the plurality of latches is selectively set or reset depending on the content of a selected cell.
A method for operating a flash memory device comprising:
- (a) selecting a memory cell;
- (b) reading cell current for the selected cell to determine a level of threshold voltage for the cell;
- (c) setting or resetting a state of a latch coupled to the selected memory cell depending on the level of the threshold voltage;
- and
- (d) erasing the selected memory cell by applying the state of the latch to the selected memory cell.
A flash memory device comprising:
- a plurality of memory cells each having a gate terminal, a source terminal and a drain terminal, the memory cells being arranged in a plurality of rows and columns,
- wherein gate terminals of memory cells in each row couple to a respective word line, drain terminals of memory cells in each column couple to a respective bit line, and source terminals of the plurality of memory cells in each row couple to a common source line, and
- wherein common source lines from N adjacent rows of memory cells couple to an electrically independent common source line to form a plurality of electrically independent common source lines;
- and
- a plurality of source line select transistors respectively coupled to the plurality of electrically independent common source lines, the plurality of source line select transistors being selectively activated during sensing operations.
A flash memory device comprising:
- a plurality of memory cells arranged in a two-dimensional array of rows and columns;
- a plurality of latches respectively coupled to the plurality of rows of memory cells;
- a first decoder coupled to the plurality of columns;
- a sense amplifier having an input coupled to the first decoder an output;
- and
- a second decoder having an input coupled to the output of the sense amplifier and a plurality of outputs respectively coupled to a plurality of set/reset inputs of the plurality of latches,
- wherein, each of the plurality of latches is selectively set or reset depending on the content of a selected cell.
Dependencies are inferred from the claim text.