MOS buffer immun to ESD damage

A buffer integrated with an ESD protection circuit onto a semiconductor substrate, said ESD protection circuit being triggered by means of a MOS-like device having a first spreading resistance during an ESD event, said buffer comprising:

• at least one source region and a plurality of drain regions alternately formed in said semiconductor substrate;
• a plurality of gate structures formed on said semiconductor substrate between each said drain region and said at least source region, respectively;
• and
• a doped region formed in said at least one source region;
• wherein said at least source region, gate structures, and drain regions constitute finger-type devices, each said finger-type device having a second spreading resistance less than said first spreading resistance.