Non-volatile memory using ferroelectric capacitor
AssigneeRohm Co., Ltd.
InventorTakashi Nakamura
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Abstract
A non-volatile memory includes a ferroelectric transistor with a gate electrode stacked through at least a first ferroelectric film on the surface of a semiconductor substrate between source/drain regions, and a ferroelectric capacitor that includes first and second electrodes, and a second ferroelectric layer sandwiched between the electrodes. The first electrode is connected to one of the source/drain regions and has a first potential difference generated between the electrode and the semiconductor substrate to invert polarization of the first ferroelectric layer, and a second potential difference generated between the first and the second electrode to invert polarization of the second ferroelectric layer so that write and read of data are executed.
Claims11
A non-volatile memory comprising:
- a ferroelectric transistor including a gate electrode stacked through at least a first ferroelectric layer on a surface of a semiconductor substrate between source/drain regions formed therein;
- and
- a ferroelectric capacitor including a first electrode and a second electrode, and a second ferroelectric layer sandwiched between the first electrode and the second electrode, the first electrode being connected to one of the source/drain regions, wherein a first potential difference is generated between the gate electrode and the semiconductor substrate to invert a polarization of the first ferroelectric layer, and a second potential difference is generated between the first electrode and the second electrode to invert a polarization of the second ferroelectric layer so that write and read of data of multilevel values are executed.
The non-volatile memory according to clam 4, wherein the second electrode includes a two layer film of iridium and iridium oxide.
A non-volatile memory comprising:
- a ferroelectric transistor including a gate electrode stacked through a first ferroelectric layer on a surface of a semiconductor substrate between source/drain regions formed therein,
- wherein the gate electrode comprises a first electrode and a second electrode, and a second ferroelectric layer sandwiched between the first electrode and the second electrode,
- wherein voltages applied to the first electrode and the second electrode are controllable independently,
- wherein a first potential difference is generated between the gate electrode and the semiconductor substrate to invert a polarization of the first ferroelectric layer, and
- wherein a second potential difference is generated between the first electrode and the second electrode to invert a polarization of the second ferroelectric layer so that write and read of data of multilevel values are executed.
Dependencies are inferred from the claim text.