Frequency divider, a phase lock oscillator and a flip-flop circuit using the frequency divider

A frequency divider comprising:

• first and second basic gates, each including first and second pairs of emitter-coupled differential transistors, and first and second emitter followers to which common collector outputs of the first and second pairs of emitter-coupled differential transistors are input, and outputs of which are respectively connected to bases of the second pair of emitter-coupled differential transistors,
• wherein common collector outputs of the first and second pairs of emitter-coupled differential transistors of the first basic gate are respectively directly input to bases of the first pair of emitter-coupled transistors of the second basic gate, and common collector outputs of the first and second pairs of emitter-coupled transistors of the second basic gate are respectively fed back to bases of the first pair of emitter-coupled differential transistors of the first basic gate;
• a third pair of emitter-coupled differential transistors, collectors of which are connected to common emitters of the first pairs of emitter-coupled differential transistors of the first and second basic gates;
• a first current source connected to a common emitter of the third pair of emitter-coupled differential transistors;
• and
• second and third current sources respectively connected to common emitters of the second pairs of emitter-coupled differential transistors of the first and second basic gates,
• wherein a differential input signal is input to bases of the third pair of emitter-coupled differential transistors and a frequency-divided differential output signal is obtained from the first and second emitter followers of the second basic gate.

A frequency divider comprising:

• first and second basic gates, each including first to third pairs of emitter-coupled differential transistors, and first and second emitter followers to which common corrector outputs of the first to third pairs of emitter-coupled differential transistors are input, and outputs of which are input to bases of the third pair of emitter-coupled differential transistors, wherein outputs of the first and second emitter followers of the first basic gate are respectively connected to bases of the first pair of emitter-coupled transistors of the second basic gate, and outputs of the first and second emitter followers of the second basic gate are respectively fed back to bases of the first pair of emitter-coupled differential transistors of the first basic gate;
• a fourth pair of emitter-coupled differential transistors, collectors of which are connected to common emitters of the first pairs of emitter-coupled differential transistors of the first and second basic gates;
• a first current source connected to a common emitter of the fourth pair of emitter-coupled differential transistors;
• a fifth pair of emitter-coupled differential transistors, collectors of which are connected to common emitters of the second pairs of emitter-coupled differential transistors of the first and second basic gates;
• a second current source connected to a common emitter of the fifth pair of emitter-coupled differential transistors;
• and
• third and fourth current sources respectively connected to common emitters of the third pairs of emitter-coupled differential transistors of the first and second basic gates,
• wherein a differential input signal is input to bases of the fourth and fifth pairs of emitter-coupled differential transistors and a frequency-divided differential output signal is obtained from the first and second emitter followers of the second basic gate.

A flip-flop circuit comprising:

• first and second basic gates, each including first to third pairs of emitter-coupled differential transistors, and first and second emitter followers to which common corrector outputs of the first to third pairs of emitter-coupled differential transistors are input, and outputs of which are respectively input to bases of the second pair of emitter-coupled differential transistors, wherein common collector outputs of the first to third pairs of emitter-coupled differential transistors of the first basic gate are respectively input to bases of the first pair of emitter-coupled transistors of the second basic gate;
• a fourth pair of emitter-coupled differential transistors, collectors of which are respectively connected to common emitters of the first pairs of emitter-coupled differential transistors of the first and second basic gates;
• a first current source connected to a common emitter of the fourth pair of emitter-coupled differential transistors;
• second and third current sources respectively connected to common emitters of the second pairs of emitter-coupled differential transistors of the first and second basic gates;
• a fifth pair of emitter-coupled differential transistors, collectors of which are respectively connected to common emitters of the third pairs of emitter-coupled differential transistors of the first and second basic gates;
• and
• a fourth current source connected to a common emitter of the fifth pair of emitter-coupled differential transistor,
• wherein a clock signal is input to bases of the fourth and fifth pairs of emitter-coupled differential transistors, data is input to the first pair of emitter coupled differential transistors of the first basic gate, and an output signal is obtained from the first and second emitter followers of the second basic gate.