Device and method for limiting the extent to which circuits in integrated circuit dice electrically load bond pads and other circuit nodes in the dice

An integrated circuit die comprising:

• a plurality of terminals for communication with circuitry external to the die;
• a plurality of load circuits capable of electrically loading the plurality of terminals such that at least one of the terminals of the plurality of terminals is loaded with more of the load circuits of the plurality of load circuits than the rest of the terminals of the plurality of terminals;
• and
• a plurality of programmable circuits, each coupled between the at least one terminal capable of being loaded with more of the load circuits of the plurality of load circuits and a corresponding one of the load circuits of the plurality of load circuits capable of loading said at least one terminal, the plurality of programmable circuits of the plurality of load circuits being configurable to isolate said at least one terminal from at least some of the load circuits of the plurality of load circuits capable of loading said at least one terminal to reduce the electrical load in said at least one terminal to be substantially the same as the electrical load in the remaining terminals of the plurality of terminals.

An integrated circuit die comprising:

• a plurality of terminals for communication with circuitry external to the die;
• a plurality of load circuits capable of electrically loading the plurality of terminals such that at least one terminal of the plurality of terminals is loaded with more of the plurality of load circuits than the remaining terminals of said plurality of terminals;
• and
• a plurality of programmable circuits, each coupled between the at least one terminal capable of being loaded with more of the plurality of load circuits and a corresponding one of the plurality of load circuits capable of loading said at least one terminal, the plurality of programmable circuits being configured to isolate said at least one terminal from at least some of the plurality of load circuits capable of loading said at least one terminal to reduce the electrical load in said at least one terminal to be substantially the same as the electrical load in the remaining terminals.

A semiconductor wafer comprising at least one integrated circuit comprising:

• a plurality of terminals for communication with circuitry external to the at least one integrated circuit;
• a plurality of load circuits constructed to electrically load the plurality of terminals such that at least one of the terminals of the plurality of terminals is loaded with more of the load circuits of the plurality of load circuits than the rest of the terminals;
• and
• a plurality of programmable circuits, each coupled between the at least one terminal of the plurality of terminals constructed to be loaded with more of the load circuits of the plurality of load circuits and a corresponding one of the load circuits of the plurality of load circuits constructed to load said at least one terminal, the plurality of programmable circuits being configurable to isolate said at least one terminal from at least some of the load circuits of the plurality of load circuits constructed to load said at least one terminal to reduce the electrical load in the at least one terminal to be substantially the same as the electrical load in the remaining terminals of the plurality of terminals.

An electronic system comprising an input device, an output device, a memory device, and a processor device coupled to the input, output, and memory devices, at least one of the input, output, memory, and processor devices comprising an integrated circuit die comprising:

• a plurality of terminals for communication with circuitry external to the die, the plurality of terminals including a first terminal;
• a plurality of load circuits constructed to electrically load the plurality of terminals, including the first terminal;
• and
• a plurality of programmable circuits, each coupled between the first terminal and a corresponding one of the plurality of load circuits constructed to load the first terminal, the plurality of programmable circuits being configurable to isolate the first terminal from at least some of the load circuits constructed to load the first terminal to reduce the electrical load in said first terminal to be substantially the same as the electrical load in the remaining terminals of the plurality of terminals.

An integrated circuit die comprising:

• a plurality of bond pads;
• a plurality of first load circuits for communicating through the bond pads in a first operating mode of the die, with each first load circuit electrically loading its respective bond pad with substantially the same electrical load;
• a second load circuit for communicating through one of the bond pads in a second operating mode of the die, with the second load circuit electrically loading its respective bond pad with an additional electrical load such that its respective bond pad has more of an electrical load than the remaining bond pads;
• a first fuse interposed between the bond pad associated with the second load circuit and the first load circuit associated with said bond pad for coupling said bond pad to said first load circuit in the first operating mode and for isolating said bond pad from said first load circuit in the second operating mode;
• and
• a second fuse interposed between said bond pad and the second load circuit for coupling said bond pad to the second load circuit in the second operating mode and for isolating said bond pad from the second load circuit in the first operating mode to reduce the electrical load on said bond pad to be substantially the same as the electrical load in the remaining bond pads.