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US 6,285,088 B1Granted
Compact memory circuit
AssigneeTexas Instruments Incorporated
InventorSudhir K. Madan
Life of this patent
Estimating the term…
Abstract
An integrated circuit having a memory cell array in which the strapping of cell components is accomplished within a memory cell. In one embodiment the strapping 750, 752, 756 is placed between the moats 706,724 of transistors that compose cross-coupled inverters within a static random access memory cell.
Claims11
An integrated circuit, comprising:
- an array of storage cells, said array comprising a series of groups of storage cells of a first type interrupted periodically by a group of storage cells of a second type, said storage cells of said second type differing from said cells of said first type in at least one aspect by comprising a contact area;
- and
- a bus disposed adjacent said array, said bus coupled to said array at said contact area.
An integrated circuit, comprising:
- an array of storage cells, said array comprising a series of columns of storage cells of a first type interrupted periodically by a column of storage cells of a second type,
- said first storage cell type including first and second transistors, said first transistor having a channel region in a first moat and said second transistor having a channel region in a second moat, said first and second moats separated by a first distance;
- said second storage cell type including third and fourth transistors, said third transistor having a channel region in a third moat and said fourth transistor having a channel region in a fourth moat, said third and fourth moats separated by a second distance, wherein said second distance is greater than said first distance.
An integrated circuit including an array of storage cells, said array comprising a series of columns of storage cells of a first type interrupted periodically by a column of storage cells of a second type,
- said first cell type including first, second, third, and fourth transistors, said first transistor having channel region formed in a first moat, said second transistor having a channel region formed in a second moat, said third transistor having a channel region formed in a third moat, and said fourth transistor having a channel region formed in a fourth moat, said first and second transistors being of the n-channel type and said third and fourth transistor being of the p-channel type, said first and second moats separated by a first distance, said third and fourth moats separated by approximately said first distance;
- said second cell type including fifth, sixth, seventh, and eighth transistors, said fifth transistor having a channel region in a fifth moat, said sixth transistor having a channel region in a sixth moat, said seventh transistor having a channel region in a seventh moat, and said eighth transistor having a channel region in an eighth moat, said fifth and sixth transistors being of the n-channel type and said seventh and eighth transistors being of the p-channel type, said fifth and sixth moats separated by a second distance, said seventh and eighth moats separated by approximately said second distance, wherein said second distance is greater than said first distance.
An integrated circuit including an array of storage cells, said array comprising a series of columns of storage cells of a first type interrupted periodically by a column of storage cells of a second type,
- said first cell type including first, second, third, and fourth transistors, said first transistor having a first gate, said second transistor having a second gate, said third transistor having a third gate, and said fourth transistor having a fourth gate, said first and second transistors being of the n-channel type and said third and fourth transistor being of the p-channel type, said first and second gates separated by a first distance, said third and fourth gates separated by approximately said first distance;
- said second cell type including fifth, sixth, seventh, and eighth transistors, said fifth transistor having a fifth gate, said sixth transistor having a sixth gate, said seventh transistor having a seventh gate, and said eighth transistor having an eighth gate, said fifth and sixth transistors being of the n-channel type and said seventh and eighth transistors being of the p-channel type, said fifth and sixth gates separated by a second distance, said seventh and eighth moats separated by approximately said second distance, wherein said second distance is greater than said first distance.
Dependencies are inferred from the claim text.