Contact structure and method of formation

A contact structure in an integrated circuit comprising:

• a semiconductor substrate having a major surface;
• a trench isolation region lying within a first portion of the semiconductor substrate, the trench isolation region comprising a trench having a trench sidewall;
• a first field effect transistor, the first field effect transistor having a source/drain electrode lying within a second portion of the semiconductor substrate, the source/drain electrode having a first portion and a second portion, the first portion having a first depth and a first width and the second portion having a second depth and a second width, wherein the first depth is greater than the second depth and the first width is less than the second width, and the first portion of the source/drain electrode abuts the trench sidewall;
• and
• a second field effect transistor having a gate electrode, the gate electrode having a first portion that lies within the trench and abuts the trench sidewall, wherein the first portion of the gate electrode is electrically shorted to the first portion of the source/drain electrode of the first field effect transistor.

A contact structure in an integrated circuit comprising:

• a semiconductor substrate having a major surface;
• a trench lying within a first portion of the semiconductor substrate, the trench having a trench sidewall;
• a first field effect transistor having a source/drain electrode lying within a second portion of the semiconductor substrate, the source/drain electrode having a first portion with a first depth and a second portion with a second depth, wherein the first depth is greater than the second depth, and the first portion of the source/drain electrode abuts the trench sidewall;
• a dielectric plug lying within the trench and substantially filling the trench;
• and
• a second field effect transistor having a gate electrode comprising a first polysilicon layer underlying a second polysilicon layer, the gate electrode overlying the dielectric plug and having a first portion extending into the trench and abutting the trench sidewall, wherein the first portion of the gate electrode is electrically shorted to the first portion of the source/drain electrode of the first field effect transistor.

A contact structure in an integrated circuit comprising:

• a semiconductor substrate having a major surface;
• a trench lying within a first portion of the semiconductor substrate, the trench having a trench sidewall;
• a first field effect transistor having a source/drain electrode lying within a second portion of the semiconductor substrate, the source/drain electrode having a first portion with a first depth and a second portion with a second depth, wherein the first depth is greater than the second depth, and the first portion of the source/drain electrode abuts the trench sidewall;
• a dielectric plug lying within the trench and substantially filling the trench;
• and
• a conductive member overlying the dielectric plug, the conductive member having a first portion lying within the trench and abutting the trench sidewall, wherein the first portion of the conductive member is electrically shorted to the first portion of the source/drain electrode of the first field effect transistor.

A contact structure in an integrated circuit comprising:

• a semiconductor substrate having a major surface;
• a trench isolation region lying within a first portion of the semiconductor substrate, the trench isolation region comprising a trench having a trench sidewall;
• a first field effect transistor having a source/drain electrode lying within a second portion of the semiconductor substrate, the source/drain electrode having a first portion with a first depth and a second portion with a second depth, wherein the first depth is greater than the second depth, and the first portion of the source/drain electrode abuts the trench sidewall;
• and
• a second field effect transistor having a gate electrode overlying the trench isolation region, the gate electrode having a first portion lying within the trench and abutting the trench sidewall, wherein the first portion of the gate electrode is electrically shorted to the first portion of the source/drain electrode of the first field effect transistor.