Method of forming semiconductor die with integral decoupling capacitor
AssigneeMicron Technology, Inc.
InventorsDavid J. Corisis, Jerry M. Brooks
Life of this patent
Estimating the term…
Abstract
A gateway or circuit barrier capacitor incorporated in a semiconductor die structure in lieu of a discrete capacitor employed with such a die in a Chip on Board assembly such as a single in-line memory module (SIMM). The capacitor may comprise a single layer with laterally adjacent, dielectrically-separated electrode traces, or a more traditional vertically-superimposed electrode design with an intervening dielectric layer. The capacitor is preferably formed using the existing fabrication process for the die by altering a photoresist mask to define the electrode traces in the same step as other conductors, such as bond pads, are formed.
Claims19
A capacitor for use with a semiconductor die, comprising:
- first and second elongated, substantially unbranched, nonlinear, planar electrodes formed as an integral portion of said semiconductor die, said electrodes formed of a metal the same as that of at least one other component disposed on an active surface of said semiconductor die, said active surface having a plurality of bumped bond pads disposed thereon, said electrodes located adjacent said active surface in an area peripheral to each of said plurality bumped bond pads;
- said electrodes occupying a common plane in substantially mutually coextensive side-by-side relationship with edges of said first electrode spaced from adjacent edges of said second electrode to define an elongated, continuous space therebetween;
- and
- a dielectric within said elongated, continuous space.
A semiconductor die, including:
- a plurality of active devices within an active surface of said semiconductor die;
- a plurality of bumped bond pads disposed on said active surface;
- a plurality of conductors extending to said plurality of bumped bond pads;
- and
- a decoupling capacitor comprising first and second elongated, substantially unbranched, nonlinear, mutually adjacent electrodes formed as an integral part of at least a portion of said active surface of said semiconductor die and in electrical communication with at least one active device of said plurality of active devices internally to said semiconductor die, said electrodes located in an area peripheral to each of said plurality of bumped bond pads, said decoupling capacitor configured to extend around said plurality of active devices, said plurality of conductors and said plurality of bond pads to occupy otherwise unoccupied real estate on said active surface.
A semiconductor die, comprising:
- at least one active surface with a plurality of bumped bond pads thereon, at least some of the plurality of bumped bond pads located inside a peripheral area of said semiconductor die;
- first and second elongated, substantially unbranched, nonlinear, planar electrodes formed integrally with said semiconductor die and located adjacent said at least one active surface of said semiconductor die, said electrodes located in an area peripheral to each of said plurality bumped bond pads, said electrodes formed of a same metal as said bond pads of said plurality of bumped bond pads;
- said electrodes occupying a common plane in substantially mutually coextensive side-by-side relationship with edges of said first electrode spaced from adjacent edges of said second electrode to define an elongated, continuous space therebetween;
- and
- a dielectric within said elongated, continuous space.
Dependencies are inferred from the claim text.