Insulated gate semiconductor device and method of manufacturing the same

A method of manufacturing an insulated gate semiconductor device comprising:

• a step of preparing a semiconductor substrate (90) defining an upper main surface and a lower main surface and including a first semiconductor layer (2) of a first conductivity type which is exposed to said upper main surface;
• a step of selectively forming a second semiconductor layer (22) of a second conductivity type in a portion of said upper main surface in said first semiconductor layer by selectively introducing an impurity of said second conductivity type into said upper main surface;
• a third semiconductor layer forming step of selectively forming a third semiconductor layer (23) of said first conductivity type having a higher impurity concentration than an impurity concentration in said first semiconductor layer in a portion of said upper main surface in said second semiconductor layer by selectively introducing an impurity of said first conductivity type into said upper main surface;
• a trench forming step of selectively forming, in said semiconductor substrate, a trench (6) reaching said first semiconductor layer through said third and second semiconductor layers by selectively performing etching on said upper main surface;
• a step of forming an insulating film (8, 17, 4) covering an internal wall of said trench and said upper main surface;
• a step of depositing a conductive layer (38) to cover said insulating film;
• a gate forming step of, by selectively removing said conductive layer, forming a gate electrode (7) buried in said trench through said insulating film, a first gate wiring (9) which is selectively provided both on said gate electrode apart from an edge of said trench along its longitudinal direction and on said insulating film covering said upper main surface and is continuously provided integrally with said gate electrode, and a second gate wiring (10) provided over said upper main surface through said insulating film opposite to said first gate wiring apart from said edge of said trench;
• a step of depositing an insulating layer (11, 18, 19) to cover said first and second gate wirings;
• a step of selectively forming a first opening (20, 40, 41) and a second opening (21) over said first and second gate wirings in said insulating layer, respectively;
• a step of forming a connecting wiring (13) which electrically connects said first gate wiring and said second gate wiring by covering said insulating layer and filling in said first and second openings;
• and
• a main electrode forming step of forming a pair of main electrodes (14, 15) to be electrically connected to a surface of said semiconductor substrate, respectively,
• wherein one of said pair of main electrodes (14) is formed to be electrically connected to said second and third semiconductor layers on said upper main surface at said main electrode forming step, and
• said gate electrode is formed such that an upper surface of said gate electrode is positioned on the same plane with said upper main surface or therebelow in a portion which is in contact with said edge of said trench at said gate forming step.

A method of manufacturing an insulated gate semiconductor device comprising:

• a step of preparing a semiconductor substrate (90) defining an upper main surface and a lower main surface and including a first semiconductor layer (2) of a first conductivity type which is exposed to said upper main surface;
• a step of selectively forming a second semiconductor layer (22) of a second conductivity type in a portion of said upper main surface in said first semiconductor layer by selectively introducing an impurity of said second conductivity type into said upper main surface;
• a third semiconductor layer forming step of selectively forming a third semiconductor layer (23) of said first conductivity type having a higher impurity concentration than an impurity concentration in said first semiconductor layer in a portion of said upper main surface in said second semiconductor layer by selectively introducing an impurity of said first conductivity type into said upper main surface;
• a trench forming step of selectively forming, in said semiconductor substrate, a trench (6) reaching said first semiconductor layer through said third and second semiconductor layers by selectively performing etching on said upper main surface;
• a step of forming an insulating film (8, 17, 4) covering an internal wall of said trench and said upper main surface;
• a step of depositing a conductive layer (38) to cover said insulating film;
• a gate forming step of, by selectively removing said conductive layer, forming a gate electrode (7) buried in said trench through said insulating film, a first gate wiring (9) which is selectively provided both on said gate electrode apart from an edge of said trench along its longitudinal direction and on said insulating film covering said upper main surface and is continuously provided integrally with said gate electrode, a second gate wiring (10) provided over said upper main surface through said insulating film opposite to said first gate wiring apart from said edge of said trench, and a connecting wiring (93) provided over said upper main surface through said insulating film apart from said edge of said trench and continuously provided integrally with said first and second gate wirings;
• and
• a main electrode forming step of forming a pair of main electrodes (14, 15) to be electrically connected to a surface of said semiconductor substrate, respectively,
• wherein one of said pair of main electrodes (14) is formed to be electrically connected to said second and third semiconductor layers on said upper main surface at said main electrode forming step, and
• said gate electrode is formed such that an upper surface of said gate electrode is positioned on the same plane with said upper main surface or therebelow in a portion which is in contact with said edge of said trench at said gate forming step.