Controlling improvement of critical dimension of dual damasceue process using spin-on-glass process
AssigneeUnited Microelectronics Corp.
InventorsYeong-Chih Lai, Yu-Tai Tsai, Chien-Chung Huang, Huang-Hui Wu
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Abstract
The present invention provides a method for controlling the critical dimension of a mask in dual damascene process. The method comprises providing a semiconductor structure which has a contact pattern thereon. A dielectric layer, such as a spin-on glass layer, is formed on the semiconductor structure and the contact pattern. Then a photoresist layer is formed on the dielectric layer. Next, the photoresist layer and the dielectric layer are etched to expose partial the semiconductor structure. Then the exposed semiconductor structure is removed followed by removing the total photoresist layer and the total dielectric layer.
Claims10
A method of controlling the critical dimension of a mask in dual damascene process, the method of comprising:
- providing a semiconductor structure, said semiconductor structure having a contact pattern thereon;
- forming a dielectric layer on said semiconductor structure and said contact pattern;
- forming a photoresist layer on said dielectric layer;
- etching said photoresist layer and said dielectric layer to expose partial said semiconductor structure;
- removing said exposed semiconductor structure;
- removing total said photoresist layer;
- and
- removing total said dielectric layer.
A method for controlling the critical dimension of a mask in dual damascene process, the method comprising:
- providing a semiconductor structure, said semiconductor having a substrate and first dielectric layer thereon;
- forming a second dielectric layer on said first dielectric layer, said second dielectric layer having a contact pattern to expose partial said first dielectric layer;
- forming a third dielectric layer on said second dielectric layer, said third dielectric layer having said contact pattern to expose partial said first dielectric layer;
- spinning-on a glass layer on said exposed first dielectric layer, a plurality of first side walls of said second dielectric layer, and a plurality of second side walls and surface of said third dielectric layer;
- forming a photoresist layer on said glass layer;
- etching said photoresist layer and said glass layer to expose partial said first dielectric layer;
- removing exposed said first dielectric layer to expose partial said substrate;
- removing said photoresist layer;
- and
- removing said glass layer to expose patterned said first side walls of said second dielectric layer and said second side walls and said surface of said third dielectric layer.
Dependencies are inferred from the claim text.