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US 6,284,642 B1Granted
Integrated method of damascene and borderless via process
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMeng-Chang Liu, Chao-Bao Cheng, Kuo-Chin Hsu
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Abstract
A new process is provided to create openings and interconnect patterns for the dual damascene structure. Four layers of dielectric are sequentially deposited over a pattern of interconnect metal. The via hole pattern is defined, the interconnect line pattern is next defined. The via pattern is etched though the upper layer of dielectric and through the stop layer. Only one etch processing step is used to create the desired vias and the desired interconnect line pattern. After the interconnect patterns and vias have been created in the four layers of dielectric, a barrier layer is blanket deposited, the metal is deposited for the dual damascene structure and the interconnect line pattern and polished.
Claims28
A method of forming a damascene structure over a semiconductor surface, comprising the steps of:
- providing a semiconductor substrate, the substrate having been provided with points of electrical interconnect in or on the surface thereof;
- depositing a first layer of dielectric over the surface of the substrate;
- depositing a first etch stop layer over the surface of the first layer of dielectric;
- depositing a second layer of dielectric over the surface of said first etch stop layer;
- depositing a second etch stop layer over the surface of the second layer of dielectric;
- patterning and etching said second etch stop layer, creating a via pattern having a via width through said second etch stop layer;
- patterning and etching a layer of etch resistant material over the surface of said second etch stop layer, creating an opening in said layer of etch stop material that aligns with said via pattern having an interconnect line width, further creating al least one opening having an interconnect line width in said layer of etch resistant material that does not align with said via pattern;
- performing a first etch, said first etch extending said width of said via pattern created in said second etch stop layer to a width of a interconnect line pattern, said first etch etching said via pattern created in said second etch stop layer through said second layer of dielectric, through said first etch stop layer and partially into said first layer of dielectric, said first etch further etching said second etch stop layer in accordance with said at least one opening created in said etch resistant material that does not align with said via pattern;
- and
- performing a second etch, said second etch further etching said via partially etched into said first layer of dielectric through said first layer of dielectric down to the surface of said substrate, said second etch further etching said interconnect line pattern through said second layer of dielectric and partially through said first etch stop layer, completing the creation of said damascene structure, said second etch further etching said second layer of dielectric in accordance with said at least one opening created in said etch resistant material that does not align with said via pattern.
7 more elements
A method of forming multi-level coplanar conductor and insulator films on a substrate, said substrate having a conductor pattern, comprising the steps of:
- providing a substrate, said substrate having metalization in or on the surface thereof;
- depositing a multiplicity of dielectric layers over the surface of said substrate, said multiplicity of dielectric layers comprising a first sub-set of dielectric layers in addition to a second sub-set of dielectric layers, said first sub-set of said multiple dielectric layers being deposited over the surface of said substrate, said second sub-set of said dielectric layers being deposited over the surface of said first sub-set of dielectric layers, said second sub-set of dielectric layers comprising an upper dielectric layer, said upper dielectric layer exposing the surface of said second sub-set of dielectric layers;
- defining and etching a via pattern through said upper dielectric layer of said multiplicity of dielectric layers;
- performing a first etch of said multiplicity of dielectric layers, said first etch etching said via pattern defined in said upper dielectric layer through said second sub-set of said multiple dielectric layers and partially into a bottom layer of said first sub-set of said multiple dielectric layers, said first etch further converting said via pattern in said upper layer of said second sub-set of dielectric layers into an interconnect line pattern in said upper dielectric layer of said multiplicity of dielectric layers;
- performing a second etch of said multiplicity of dielectric layers, said second etch further etching said via pattern etched through said second sub-set of said multiple dielectric layers and partially into said first sub-set of said multiple dielectric layers through said first sub-set of said multiple dielectric layers, creating a via opening through said first sub-set of said multiple dielectric layers, said second etch further etching said interconnect line pattern in said upper dielectric of said multiplicity of dielectric layers through said second sub-set of said multiplicity of dielectric layers, creating an interconnect line pattern opening through said second sub-set of said multiplicity of dielectric layers;
- depositing a barrier layer over said via opening and said interconnect line pattern opening, including the surface of said upper layer of dielectric;
- depositing a layer of metal over said barrier layer;
- and
- removing excess metal from the surface of said upper layer of dielectric.
6 more elements
Dependencies are inferred from the claim text.