Method to fabricate a floating gate with a sloping sidewall for a flash memory

A method for fabrication of stacked gate structure for a Flash EEPROM cell:

• providing a semiconductor substrate;
• providing field oxide isolation regions in said substrate;
• providing a tunneling oxide layer overlying said isolation regions and said substrate;
• depositing a first polysilicon layer overlying said tunneling oxide layer;
• forming a photoresist mask overlying said first polysilicon layer;
• isotropically etching away said first polysilicon layer and said tunneling oxide layer in areas not covered by said photoresist mask to create said floating gates with outwardly sloping sidewall edges that intersect said isolation regions at an obtuse angle of between 95 and 105 degrees wherein etching gases for said etching consist of Cl2, CF4, HBr, and O2;
• etching away said photoresist layer;
• depositing an interpoly dielectric layer overlying said floating gates, said sloping sidewall edges, and said isolation regions;
• depositing a second polysilicon layer overlying said interpoly dielectric;
• and
• completing said fabrication of stacked gate structures in said Flash EEPROM cells.

A method for fabrication of stacked gate structure for a Flash EEPROM cell:

• providing a semiconductor substrate;
• providing field oxide isolation regions in said substrate;
• providing a tunneling oxide layer overlying said isolation regions and said substrate;
• depositing a first polysilicon layer overlying said tunneling oxide layer;
• isotropically etching away said first polysilicon layer and said tunneling oxide layer in areas not covered by said photoresist mask to create said floating gates with outwardly sloping sidewall edges that intersect said isolation regions at an obtuse angle of between 95 and 105 degrees using a reactive ion etch process consisting of Cl2 gas flowed at between 50 and 150 SCCM, CF4 gas flowed at between 50 and 150 SCCM, HBr gas flowed at between 50 and 150 SCCM, and O2 gas flowed at between about 1 and 5 SCCM, a pressure of between 5 and 20 milliTorr, and plasma generation using Tcp coil with a top coil power range between 100 and 250 watts and a bottom bias power range of between 50 and 150 watts;
• etching away said photoresist layer;
• depositing an interpoly dielectric layer overlying said floating gates, said sloping sidewall edges, and said isolation regions;
• depositing a second polysilicon layer overlying said interpoly dielectric;
• and
• completing said fabrication of stacked gate structures in said Flash EEPROM cells.