Species implantation for minimizing interface defect density in flash memory devices

A method for minimizing degradation of an interface between a bit line junction and a control dielectric structure during program or erase operations of a flash memory device, the method including the steps of:

• A. patterning a semiconductor wafer having a control dielectric stack thereon to expose a bit line area and to mask a control gate area of said semiconductor wafer, wherein said control dielectric stack is comprised of a first silicon dioxide (SiO2) layer on said semiconductor wafer, a silicon nitride (SiN) layer on said first silicon dioxide (SiO2) layer, and a second silicon dioxide (SiO2) layer on said silicon nitride (SiN) layer;
• B. implanting a junction dopant into said exposed bit line area to form said bit line junction in said bit line area of said semiconductor wafer, wherein said junction dopant is comprised of one of arsenic (As) or phosphorous (P);
• C. implanting nitrogen into said exposed bit line area, and wherein said nitrogen is implanted into said exposed bit line area with a concentration in a range of from about 3×1020 per cm3 to about 2×1021/cm3;
• D. patterning said control dielectric stack such that said control dielectric stack is removed from said exposed bit line area and such that said control dielectric stack remains at said control gate area to form said control dielectric structure;
• and
• E. performing a thermal process that heats up said semiconductor wafer, and wherein said thermal process is for forming a field oxide at the bit line junction area to electrically isolate said control dielectric structure;
• and wherein said bit line junction extends under said control dielectric structure from thermal diffusion of said junction dopant to form said interface between said bit line junction and said control dielectric structure, and wherein said junction dopant is implanted into said exposed bit line area at an angle in said step B to ensure that said bit line junction extends under said control dielectric structure;
• and wherein said nitrogen implanted within said semiconductor wafer thermally drifts to said interface between said bit line junction and said control dielectric structure during said thermal process, and wherein said nitrogen is implanted into said exposed bit line area at an angle in said step C to ensure that said nitrogen drifts to said interface between said bit line junction and said control dielectric structure, and wherein said nitrogen at said interface minimizes formation of interface defects at said interface during hot carrier injection through said interface.