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AssigneeLSI Logic Corporation
InventorsJohn J. Seliskar, Derryl D. J. Allman, John W. Gregory, James P. Yakura, Dim Lee Kwong
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The present invention relates to a semiconductor device, preferably a capacitor, and a method of forming the same. The method adds only a single additional masking step to the the fabrication process and reduces problems relating to alignment of various layers. A relatively thick insulation layer is formed over a bottom electrode. An opening having a sidewall that is etched in the insulation layer using a mask to expose a portion of the bottom electrode. Once the mask is removed, a dielectric layer and conductive layer are then sequentially deposited over the entire structure, including sidewalls. Thereafter, chemical-mechanical polishing is used to remove portions of the conductive layer and the dielectric layer so that the conductive layer and dielectric layer which remains forms, for example, the top electrode and dielectric layer of the integrated circuit capacitor. The top electrode is thus disposed above a central region which remains of the dielectric layer and between a peripheral region which remains of the dielectric layer.
A method of making a dielectric layer and a top electrode of an integrated circuit capacitor using only a single masking layer comprising the steps of:
A method of making an integrated circuit having a capacitor embedded at one of a plural number of layers above a substrate comprising the steps of:
Dependencies are inferred from the claim text.