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US 6,281,103 B1Granted
Method for fabricating gate semiconductor
AssigneeMicron Technology, Inc.
InventorTrung Tri Doan
Life of this patent
Estimating the term…
Abstract
A method for fabricating floating gate semiconductor devices, such as flash EEPROMs, and flash EEPROM memory arrays, is provided. The method includes providing a semiconductor substrate and forming active areas on the substrate. Each active area includes elements of a field effect transistor (FET) including a source, a drain, a channel region, and a gate dielectric layer. Trench isolation structures are also formed in the substrate for electrically isolating the active areas. In addition, a conducive layer (e.g., polysilicon) is deposited on the active areas, and chemically mechanically planarized to an endpoint of the trench isolation structures to form self aligned floating gates on the active areas. Control gate dielectric layers, and control gates are then formed on the floating gates.
Claims20
A method for fabricating a semiconductor device comprising:
- providing a substrate comprising an active area and a first surface;
- forming spaced isolation structures in the substrate having second surfaces spaced from the first surface, the isolation structures configured to electrically isolate the active area and to form a recess at least partially enclosing the active area;
- forming a dielectric layer on the first surface and in the recess;
- forming a conductive layer comprising a conductive material on the second surfaces, on the dielectric layer and in the recess;
- planarizing the conductive layer to the second surfaces to remove the conductive material except in the recess to at least partially define a floating gate in the recess and on the active area;
- and
- forming a control gate on the floating gate.
4 more elements
A method for fabricating a semiconductor device comprising:
- providing a substrate comprising an active area and a first surface;
- forming a mask on the first surface having a thickness and comprising a plurality of openings;
- forming spaced isolation structures in the openings and in the substrate comprising an electrically insulating layer having a second surface spaced from the first surface by a height equal to the thickness, the isolation structures configured to electrically isolate the active area and to form a recess at least partially enclosing the active area;
- forming a dielectric layer in the recess and on the first surface;
- forming a conductive layer on the dielectric layer, and on the second surface;
- and
- planarizing the conductive layer to the second surface to at least partially define a floating gate in the recess.
4 more elements
A method for fabricating a semiconductor device comprising:
- providing a substrate comprising an active area having a first surface, a first side and a second side;
- forming a first isolation structure in the substrate proximate to the first side and a second isolation structure proximate to the second side, the first isolation structure and the second isolation structure comprising an electrically insulating oxide having a second surface spaced from the first surface to define a recess at least partially enclosing the active area;
- forming a first dielectric layer on the active area;
- forming a conductive layer in the recess and on the second surface;
- chemically mechanically planarizing and removing the conductive layer to the second surface to at least partially define a floating gate on the active area.
2 more elements
A method for fabricating a semiconductor device comprising:
- providing a substrate comprising an active area having a surface, a first side and a second side;
- forming a first isolation structure in the substrate on the first side, and a second isolation structure in the substrate on the second side, the first isolation structure and the second isolation structure comprising an electrically insulating oxide having a second surface spaced from the first surface to define a recess at least partially enclosing the active area;
- forming a gate dielectric layer on the first surface;
- forming a conductive layer in the recess, on the gate dielectric layer, and on the second surface;
- chemically mechanically planarizing the conductive layer to the second surface to at least partially define a floating gate on the active area;
- following the planarizing step, forming a control gate dielectric layer on the conductive layer;
- forming a second conductive layer on the control gate dielectric layer;
- and
- etching the second conductive layer, the control gate dielectric layer, and the conductive layer to form the floating gate with a control gate thereon.
6 more elements
A method for fabricating a semiconductor memory array comprising:
- providing a substrate having a first surface and comprising a plurality of active areas for field effect transistors;
- forming a plurality of isolation structures in the substrate configured to electrically isolate the active areas, the isolation structures comprising an electrically insulating layer patterned to form a plurality of recesses at least partially enclosing the active areas;
- forming a gate dielectric layer on the first surface;
- forming a conductive layer on the gate dielectric layer, in the recesses and on the second surface;
- planarizing and removing the conductive layer to the second surface to define self aligned floating gates in the recesses.
2 more elements
A method for fabricating a semiconductor device comprising:
- providing a substrate having a surface and comprising a plurality of active areas;
- forming a plurality of isolation structures in the substrate configured to electrically isolate the active areas, the isolation structures comprising an electrically insulating layer having a thickness patterned to formed a plurality of recesses having a depth equal to the thickness configured to at least partially enclose the active areas;
- forming a first dielectric layer on the surface of the substrate;
- forming a first conductive layer comprising a conductive material on the first dielectric layer, in the recesses and on the isolation structures;
- forming a second dielectric layer on the first conductive layer;
- planarizing the second dielectric layer to surfaces of the isolation structures;
- forming a second conductive layer on the second dielectric layer;
- and
- etching the second conductive layer, the second dielectric layer, and the first conductive layer to form control gates and floating gates on the active areas.
6 more elements
Dependencies are inferred from the claim text.