Process of forming metal silicide interconnects
AssigneeMicron Technology, Inc.
InventorRavi Iyer
Life of this patent
Estimating the term…
Abstract
A process for forming a metal silicide interconnect includes applying a layer of polysilicon over a semiconductor layer. A layer of amorphous silicon is formed over the layer of polysilicon followed by a layer of metal, such as titanium, over the layer of amorphous silicon. A second layer of amorphous silicon may also be formed over the layer of metal. The layer of titanium is reacted with the layer of amorphous silicon to form a small grain C49 layer of titanium silicide. The layer of polysilicon and the layer of titanium silicide are etched to form a desired interconnect structure. The small grain C49 layer of titanium silicide is then converted to the C54 phase.
Claims13
A process of forming an interconnect structure comprising:
- providing at least one semiconductor layer;
- forming a layer of polysilicon over said at least one semiconductor layer;
- forming a first layer of amorphous silicon over said layer of polysilicon;
- forming a layer of metal over said first layer of amorphous silicon;
- forming a second layer of amorphous silicon over said layer of metal;
- and
- reacting said first and second layers of amorphous silicon with said layer of metal to form a metal silicide structure.
A process of forming a memory array, said memory array comprising a plurality of memory cells arranged in rows and columns, each of said plurality of memory cells comprising at least one field effect transistor, said process comprising:
- providing at least one semiconductor layer;
- forming a source and a drain for each of said field effect transistors over said at least one semiconductor layer;
- forming a gate oxide for each of said field effect transistors over said at least one semiconductor layer;
- forming a layer of polysilicon over said at least one semiconductor layer;
- forming a layer of amorphous silicon over said layer of polysilicon;
- forming a layer of titanium over said layer of amorphous silicon;
- reacting said layer of amorphous silicon with said layer of titanium to form a titanium silicide structure;
- and
- patterning said titanium silicide structure for interconnecting desired gates of each of said field effect transistors and other structures formed as part of said memory array.
A process of fabricating a wafer comprising:
- providing a wafer having a substrate assembly, said substrate assembly having at least one semiconductor layer;
- forming a repeating series of sources, drains and gate oxides for at least one field effect transistor on each of a plurality of individual die on said wafer over said at least one semiconductor layer;
- forming a layer of polysilicon over said at least one semiconductor layer;
- forming a layer of amorphous silicon over said layer of polysilicon;
- forming a layer of titanium over said layer of amorphous silicon;
- reacting said layer of amorphous silicon with said layer of titanium to form a titanium silicide structure;
- and
- patterning said titanium silicide structure for interconnecting desired structures on each of said plurality of individual die on said wafer.
Dependencies are inferred from the claim text.