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US 6,281,096 B1Granted
Chip scale packaging process
AssigneeInternational Rectifier Corporation
InventorPeter R. Ewer
Life of this patent
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Abstract
A process for forming a true chip scale package comprising the sandwiching of a silicon wafer with a large number of identical die therein between top and bottom metal contact plates of the same size as the wafer. The sandwich is secured together as by soldering, and the die and contact plates are singulated in the form of a final chip scale package. The edge of each chip may have an insulation band formed thereon. Slots may be formed in the top contact to define, with the edge saw cuts, a separate contact area on each top contact.
Claims14
The process of manufacturing a semiconductor device package;
- said process comprising:
- the formation of a plurality of adjacently located identical die with identical junction patterns in a single wafer of semiconductor material, said adjacently located die being separated by streets in said wafer;
- forming a top solderable metal contact and a bottom solderable metal contact on each of said die within said wafer;
- conductively affixing one surface of each of a first metal contact disk and a second metal contact disk over the full upper and full lower surfaces of said wafer respectively and in contact with said top and bottom solderable metal contacts respectively;
- and thereafter slicing vertically through said first and second metal contact disks and said wafer in said streets of said wafer, thereby separating said plurality of die and their respective top and bottom contacts from one another.
2 more elements
Dependencies are inferred from the claim text.