Method of manufacturing SRAM having enhanced cell ratio
AssigneeHyundai Electronics Industries Co., Ltd.
InventorJae-Kap Kim
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Abstract
An SRAM cell and a method of manufacturing the same are disclosed. An SRAM cell including pull down devices, access devices and pull up devices each having source and drain regions with LDD structure, the source and drain regions of the access devices having: N+ source and drain regions; N− source and drain regions formed under the N+ source and drain regions; and P− impurity regions whose predetermined portion is overlapped with the N− source and drain region.
Claims20
A method for manufacturing an SRAM cell having pull down devices, access devices and pull up devices comprising the steps of:
- providing a semiconductor substrate having an active region defined by an isolating layer, a gate insulating layer and gates formed thereon;
- respectively forming N− source device regions and drain device regions for pull down device regions and access device regions on the substrate on both sides of the gates of the pull down devices and the access devices;
- and
- forming P− impurity regions within the semiconductor substrate on both sides of the gates of the access device regions including a predetermined portion of the N− source device regions and drain device regions of the access device regions wherein the P− impurity regions overlap with the predetermined portion of the N− source device regions and drain device regions of the access device regions.
A method for manufacturing an SRAM cell having pull down devices, access devices and pull up devices comprising the steps of:
- providing a semiconductor substrate having an active region defined by an isolating layer, and a gate insulating layer and a gates formed on the semiconductor substrate;
- forming an insulating layer spacers on both side walls of the gates;
- respectively forming N− source and drain regions on the semiconductor substrate of both sides of gates of the pull down devices region and the access devices region, wherein the concentration of the N− source and drain regions is 2×1018 to 5×1018 ions/cm3;
- forming P− impurity regions within the semiconductor substrate of both sides of the gate including a predetermined portion of the N− source and drain regions of the access device, wherein the concentration of P− impurity regions is 1×1018 to 3×1018 ions/cm3, wherein the P impurity regions is overlapped with the predetermined portion of the N− source and drain regions of the access device;
- and
- forming N+ source and drain regions in the substrate of both sides of said spacers of said pull down devices region and said access devices region.
Method for forming an SRAM cell having a cell ratio defined by a ratio between a driving device current and an access device current, comprising the steps of:
- forming the SRAM cell with driving devices, access devices and pull-up devices each having source and drain regions with a lightly doped drain structure;
- and
- forming the source and drain regions of the access devices by forming first (N+) source and drain regions, second (N−) source and drain regions formed under the first source and drain regions, and impurity regions (P−) with a predetermined portion thereof overlapping the second source and drain regions such that the cell ratio is increased by reducing the access device current in relation to the driving device current.
Dependencies are inferred from the claim text.