US 6,281,082 B1 · Method to form MOS transistors with a common shallow trench isolation and interlevel dielectric gap fill

Abstract

A new method of forming MOS transistors in the manufacture of an integrated circuit device has been achieved. A semiconductor substrate is provided. A pad oxide layer is deposited. A silicon nitride layer is deposited. Trenches are patterned for planned shallow trench isolations. The sidewalls of the trenches are oxidized. A photoresist layer is deposited overlying the silicon nitride layer and filling the trenches. The photoresist layer is etched down to below the top surface of the silicon nitride layer. The silicon nitride layer is patterned to form dummy gate electrodes. Sidewall spacers are formed on the dummy gate electrodes. The photoresist layer is removed. A dielectric layer is deposited overlying the dummy gate electrodes and the trenches. The dielectric layer is polished down to the top surface of the dummy gate electrodes to thereby complete the STI and the ILD. The dummy gate electrodes are etched away. A gate oxide layer is formed. A gate electrode layer is deposited overlying the dielectric layer and filling the openings for the planned transistor gates. The gate electrode layer is polished down to form the transistor gates, and the integrated circuit is completed.

Claims20

Dependent claims

A method to form transistor gates and shallow trench isolations in the manufacture of an integrated circuit device comprising:

providing a semiconductor substrate;
depositing a pad oxide layer overlying said semiconductor substrate;
depositing a silicon nitride layer overlying said pad oxide layer;
patterning said silicon nitride layer, said pad oxide layer, and said semiconductor substrate to form trenches for planned shallow trench isolations;
depositing a photoresist layer overlying said silicon nitride layer and filling said trenches;
etching down said photoresist layer to below the top surface of said silicon nitride layer the trench remaining filled;
patterning said silicon nitride layer and said pad oxide layer to form dummy gates where said transistor gates are planned and wherein the presence of said photoresist layer protects said trenches from patterning;
removing said photoresist layer;
thereafter depositing a dielectric layer overlying said dummy gates and said trenches;
polishing down said dielectric layer to the top surface of said dummy gates to thereby form said shallow trench isolations and to form a planarized interlevel dielectric layer;
etching away said dummy gates to form openings for said planned transistor gate electrodes;
depositing a gate electrode layer overlying said dielectric layer and filling said openings for said planned transistor gate electrode;
and
polishing down said gate electrode layer to form said transistor gates and to complete said integrated circuit device.

11 more elements

A method to form MOS transistors with shallow trench isolations in the manufacture of an integrated circuit device comprising:

providing a semiconductor substrate;
depositing a pad oxide layer overlying said semiconductor substrate;
depositing a silicon nitride layer overlying said pad oxide layer;
patterning said silicon nitride layer, said pad oxide layer, and said semiconductor substrate to form trenches for planned shallow trench isolations;
depositing a photoresist layer overlying said silicon nitride layer and filling said trenches;
implanting ions into said semiconductor substrate to form transistor well junctions;
etching down said photoresist layer to below the top surface of said silicon nitride layer the trench remaining filled;
patterning said silicon nitride layer and said pad oxide layer to form dummy gates where said transistor gates are planned and wherein the presence of said photoresist layer protects said trenches from patterning;
implanting ions into said semiconductor substrate to form lightly doped drain junctions;
forming sidewall spacers on said dummy gate electrodes;
implanting ions into said semiconductor substrate to form source and drain junctions;
removing said photoresist layer;
thereafter depositing a dielectric layer overlying said dummy gates and said trenches;
polishing down said dielectric layer to the top surface of said dummy gates to thereby form said shallow trench isolations and to form a planarized interlevel dielectric layer;
etching away said dummy gates to form openings for said planned transistor gate electrodes;
depositing a gate electrode layer overlying said dielectric layer and filling said openings for said planned transistor gate electrode;
and
polishing down said gate electrode layer to form said transistor gates and to form said transistors and to complete said integrated circuit device.

15 more elements

A method to form MOS transistors with shallow trench isolations in the manufacture of an integrated circuit device comprising:

providing a semiconductor substrate;
depositing a pad oxide layer overlying said semiconductor substrate;
depositing a silicon nitride layer overlying said pad oxide layer;
patterning said silicon nitride layer, said pad oxide layer, and said semiconductor substrate to form trenches for planned shallow trench isolations;
oxidizing said trenches to form an oxide layer on the inside surfaces of said trenches;
depositing a photoresist layer overlying said silicon nitride layer and filling said trenches;
implanting ions into said semiconductor substrate to form transistor well junctions;
etching down said photoresist layer to below the top surface of said silicon nitride layer the trench remaining filled;
patterning said silicon nitride layer and said pad oxide layer to form dummy gates where said transistor gates are planned and wherein the presence of said photoresist layer protects said trenches from patterning;
implanting ions into said semiconductor substrate to form lightly doped drain junctions;
forming sidewall spacers on said dummy gate electrodes;
implanting ions into said semiconductor substrate to form source and drain junctions;
removing said photoresist layer;
thereafter depositing a dielectric layer overlying said dummy gates and said trenches wherein said dielectric layer comprises a silicon dioxide deposited by a high density plasma process;
polishing down said dielectric layer to the top surface of said dummy gates to thereby form said shallow trench isolations and to form a planarized interlevel dielectric layer;
etching away said dummy gates to form openings for said planned transistor gate electrodes;
depositing a gate electrode layer overlying said dielectric layer and filling said openings for said planned transistor gate electrode;
and
polishing down said gate electrode layer to form said transistor gates and to form said transistors and to complete said integrated circuit device.

16 more elements

Dependencies are inferred from the claim text.

Method to form MOS transistors with a common shallow trench isolation and interlevel dielectric gap fill

Life of this patent

Method to form MOS transistors with a common shallow trench isolation and interlevel dielectric gap fill

Life of this patent

Abstract

Claims20