Fabrication method in improving ESD ability and vertical BJT gain

A method for fabricating an electrostatic discharge (ESD) protection transistor, comprising:

• providing a semiconductor substrate having a first conductivity type formed with a well having a second conductivity type which is opposite to said first conductivity type;
• forming a field oxide (FOX) structure on top of a junction between said substrate and said well, a portion of which extends upward above the surface of said substrate and said well;
• forming a gate oxide layer on top of the exposed surface of said well;
• forming a polysilicon layer over the entire exposed upper surface of the resulting structure obtained after the formation of said gate oxide layer;
• selectively removing said polysilicon layer and said gate oxide layer, thereby forming a gate electrode;
• implanting impurity ions having the first conductivity type in an exposed surface portion of said well to a first depth, thereby forming n.sup.+source/drain region;
• forming an inter-layer dielectric (ILD) overlying the overall surface of said device;
• forming two contact windows through said inter-layer dielectric, each window exposing a portion of said source/drain region;
• implanting impurity ions having the first conductivity type by plugging method in said source/drain region to a second depth deeper than said first depth;
• and
• annealing the resulting structure.

A method for fabricating a metal oxide semiconductor device, comprising:

• providing a semiconductor substrate having a first conductivity type formed with a well having a second conductivity type which is opposite to said first conductivity type;
• forming two isolation regions on top of said well and an isolation region on top of a junction between said substrate and said well;
• implanting impurity ions having the first conductivity type in an exposed surface portion of said well and between said two isolation regions to a first depth, thereby forming n.sup.+emitter region;
• implanting impurity ions having the second conductivity type in the remaining exposed surface portion of said well, thereby forming p.sup.+electrodes;
• forming an inter-layer dielectric (ILD) overlying the overall surface of said device;
• forming contact windows through said inter-layer dielectric, each window exposing a portion of said emitter region and electrodes;
• implanting impurity ions having the first conductivity type by plugging method in said emitter region to a second depth deeper than said first depth;
• and
• annealing the resulting structure.