Method of manufacturing a semiconductor device containing a BiCMOS circuit
AssigneesMitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
InventorsTakayuki Igarashi, Yoshitaka Ohtsu
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Abstract
A structure of a BiCMOS transistor hindering over-etching of source/drain regions of a MOS transistor and a manufacturing method thereof are provided. A polysilicon film that is to be a gate electrode lower layer of a MOS transistor is formed, and thereon, another polysilicon film that is to be a gate electrode upper layer of the MOS transistor as well as to be a base electrode of a bipolar transistor is formed. Thereafter, etching is conducted to form the polysilicon film to be the base electrode of the bipolar transistor and the gate electrode at the same time. Here, an oxide film shown in FIG. 4 serves as a protective film, thereby hindering over-etching of n type and p type wells to be active regions of respective MOS transistors.
Claims11
A method of manufacturing a semiconductor device provided with a bipolar transistor and a field effect transistor on a semiconductor substrate, comprising the steps of:
- forming a first conductivity type collector region at least on an underside of a portion that is to become a first active region, the first active region being to be formed from a main surface of the semiconductor substrate to a prescribed depth;
- forming an element separating insulating film on the main surface of said semiconductor substrate to separately form, on said collector region, said first active region in which said bipolar transistor is to be formed, and, on a region except for said collector region, a second active region of a first conductivity type in which said field effect transistor is to be formed;
- forming first and second impurity layers of a first conductivity type in said first and second active regions, respectively;
- forming a first insulating film on the main surface of said second active region;
- forming a first conductive layer doped with impurity of a first conductivity type on said first insulating layer;
- forming a first semiconductor layer on the main surface of said first active region and on said first conductive layer;
- etching said first semiconductor layer, said first conductive layer and said first insulating film to form a layer to be a base electrode on said first active region, and to form a gate electrode consisting of a gate electrode upper layer and a gate electrode lower layer and a gate insulating film on said second active region;
- introducing a second conductivity type impurity into said layer to be the base electrode to form a base electrode, and introducing a second conductivity type impurity into said second active region to form a first impurity diffusion region;
- covering with a second insulating film said gate electrode upper layer, said gate electrode lower layer, said gate insulating film, said base electrode, and said first impurity diffusion region;
- forming an opening in said second insulating film and said base electrode;
- introducing a second conductivity type impurity from said opening into said first active region to form a second impurity diffusion region to be a base region;
- forming a sidewall insulating film on a sidewall of said opening;
- and
- forming an emitter electrode in contact with said second impurity diffusion region, to be fitted on said sidewall insulating film and an upper surface of said second insulating film.
Dependencies are inferred from the claim text.