Manufacturing method of a semiconductor device and a nonvolatile semiconductor storage device
AssigneeKabushiki Kaisha Toshiba
InventorEiji Sakagami
Life of this patent
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Abstract
A nitride film (14A) as a had pattern mask in a peripheral transistor forming region and a cell transistor forming region is narrowed by A1 into a narrower nitride film (14B) by pull-back. While the narrower oxide film (14B) in the cell transistor forming region is covered by an oxide film (22), the narrower nitride film (14B) in the peripheral transistor forming region is further narrowed by A2 into a still narrower nitride film (14C) by pull-back. By making apertures (28A, 28B) in a buried oxide film (28) by using the narrower nitride film (14B) and the still narrower nitride film (14C), STI edges made of the buried oxide film (28) can be prevented from depressing or falling down.
Claims11
A manufacturing method of a nonvolatile semiconductor storage device including a memory cell transistor forming region for forming a memory cell transistor, and a peripheral transistor forming region for forming a peripheral transistor for said memory cell transistor, comprising the steps of:
- making on a semiconductor substrate a first pattern mask having an aperture in a trench isolation forming region;
- making an isolation aperture in said semiconductor substrate by using said first pattern mask;
- narrowing the width of said first pattern mask to form a second pattern mask having a first mask with a first width in said memory cell transistor forming region and a second mask with a second width narrower than said first width in said peripheral transistor forming region;
- forming a buried insulating film which buries said isolation aperture and extends onto said pattern mask;
- removing said second pattern mask, then making a first aperture with said first width in a portion of said buried insulating film located in said memory cell transistor forming region, from which said first mask has been removed, and making a second aperture with said second width in a portion of said buried insulating film located in said peripheral transistor forming region, from which said second mask has been removed;
- forming a first insulating film with a first thickness on the bottom surface of said first aperture located in said memory cell transistor forming region and the bottom surface of said second aperture located in said peripheral transistor forming region;
- removing said first insulating film formed on the bottom surface of said second aperture located in said peripheral transistor forming region while maintaining said first insulating film formed on the bottom surface of said first aperture located in said memory cell transistor forming region;
- forming a second insulating film different in thickness from said first insulating film on the bottom surface of said second aperture located in said peripheral transistor forming region;
- removing said second insulating film formed on the bottom surface of said second aperture located in a low voltage-withstanding transistor forming region of said peripheral transistor forming region for forming a low voltage-withstanding transistor while maintaining said first insulating film formed on the bottom surface of said first aperture located in said memory cell transistor forming region and said second insulating film formed on the bottom surface of said second aperture located in a high voltage-withstanding transistor forming region of said peripheral transistor forming region for forming a high voltage-withstanding transistor;
- and
- forming a third insulating film on the bottom surface of said second aperture located in said low voltage-withstanding transistor forming region, said third insulating film having a thickness different from the thickness of said first insulating film and different from the thickness of said second insulating film located in said high voltage-withstanding transistor forming region.
A manufacturing method of a nonvolatile semiconductor storage device including a memory cell transistor forming region for forming a memory cell transistor, and a peripheral transistor forming region for forming a peripheral transistor for said memory cell transistor, comprising the steps of:
- forming a tunnel oxide film on a semiconductor substrate in said memory transistor forming region;
- forming a first oxide film on said semiconductor substrate in said peripheral transistor forming region;
- making an aperture in each trench isolation forming region in said tunnel oxide film, said first oxide film and a surface side of said semiconductor substrate to use the surface side of said semiconductor substrate located between apertures as an active region;
- conducting rounding oxidation of said semiconductor substrate to make bird's beaks which bite at least into said first oxide film portion located in said active region;
- burying a buried oxide film in said aperture in each said trench isolation forming region in said memory cell transistor forming region and said peripheral transistor forming region to make trench isolation;
- and
- removing said first oxide film from said active region in said peripheral transistor forming region.
Dependencies are inferred from the claim text.