US 6,275,413 B1Granted

Architecture of a non-volatile electrically erasable and programmable memory

AssigneeSTMicroelectronics S.r.l.

InventorDavid Naura

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Abstract

In a EEPROM memory architecture organized into word columns that includes n memory cells per word column, there is, for each word of the column, one diffusion line to connect sources of the memory cells to a ground connection transistor using a source line. A word read access includes simultaneously selecting the word accessed in a read mode in a first group of memory cells, and an additional word in the second group of memory cells. Each column has n bit lines ranked 0 to n−1, each connected to the same ranked cells in the first group of memory cells. The connection of each of the n cells ranked 0 to n−1 in the second group of memory cells to one of the n bit lines of the column are such that a length of connection between a source of a memory cell connected to an i ranked bit line in the second group of memory cells to a respective second diffusion connection corresponds to a length of connection between a source of a memory cell connected to an (n−1)-i ranked bit line in the first group of memory cells to a respective first diffusion connection.

Claims25

Dependent claims

An electrically erasable and programmable non-volatile memory comprising:

a plurality of word columns, each column comprising a first group of n memory cells ranked 0 to n−1 and a second group of n memory cells ranked 0 to n−1, the first and second groups of memory cells each comprising at least one transistor including a conduction terminal;
a first group of word lines connected to the first group of memory cells;
a second group of word lines connected to the second group of memory cells such that a read access to a word in the first group of memory cells leads to selection of a corresponding word in the second group of memory cells;
n bit lines ranked 0 to n−1 connected to the first group of memory cells having the same ranking;
a first group of diffusion connections for each column;
a first group of diffusion lines connected to the conduction terminals of the first group of memory cells via the first group of diffusion connections for each column;
a second group of diffusion connections for each column;
a second group of diffusion lines connected to the conduction terminals of the second group of memory cells via the second group of diffusion connections for each column, a length of connection between a conduction terminal of a memory cell connected to an i ranked bit line in the second group of memory cells and a respective second diffusion connection corresponding to a length of connection between a conduction terminal of a memory cell connected to an (n−1)-i ranked bit line in the first group of memory cells and a respective first diffusion connection;
and
a connection transistor connected to the first and second groups of diffusion connections for each column.

7 more elements

A memory comprising:

a plurality of word columns, each column comprising a first group of n memory cells ranked 0 to n−1 and a second group of n memory cells ranked 0 to n−1, the first and second groups of memory cells each comprising at least one transistor including a conduction terminal;
a first group of word lines connected to the first group of memory cells;
a second group of word lines connected to the second group of memory cells such that a read access to a word in the first group of memory cells leads to selection of a corresponding word in the second group of memory cells;
n bit lines ranked 0 to n−1 connected to the first and second groups of memory cells having the same ranking;
a first group of diffusion connections for each column;
a first group of diffusion lines connected to the conduction terminals of the first group of memory cells via the first group of diffusion connections for each column;
a first conducting line connected to the first group of diffusion connections for each column;
a second group of diffusion lines connected to the conduction terminals of the second group of memory cells via a second group of diffusion connections for each column, a length of connection between a conduction terminal of a memory cell connected to an i ranked bit line in the second group of memory cells and a respective second diffusion connection corresponding to a length of connection between a conduction terminal of a memory cell connected to an (n−1)-i ranked bit line in the first group of memory cells and a respective first diffusion connection;
and
a second conducting line connected to the second group of diffusion connections for each column.

7 more elements

A memory comprising:

a plurality of word columns, each column comprising a first group of n memory cells ranked 0 to n−1 and a second group of n memory cells ranked 0 to n−1, the first and second groups of memory cells each comprising at least one transistor including a conduction terminal;
a first group of word lines connected to the first group of memory cells;
a second group of word lines connected to the second group of memory cells such that a read access to a word in the first group of memory cells leads to selection of a corresponding word in the second group of memory cells;
n bit lines ranked 0 to n−1 connected to the first group of memory cells having the same ranking;
a first group of diffusion connections for each column;
a first group of diffusion lines connected to the conduction terminals of the first group of memory cells via the first group of diffusion connections for each column;
a second group of diffusion connections for each column;
a second group of diffusion lines connected to the conduction terminals of the second group of memory cells via the second group of diffusion connections for each column;
a multiplexer connected to the n bit lines between the first and second groups of memory cells for connecting an i ranked bit line connected to a memory cell in the first group of memory cells to an (n−1)-i ranked bit line connected to a memory cell in the second group of memory cells so that a length of connection between a conduction terminal of a memory cell connected to the i ranked bit line in the second group of memory cells and a respective second diffusion connection corresponding to a length of connection between a conduction terminal of a memory cell connected to an (n−1)-i ranked bit line in the first group of memory cells and a respective first diffusion connection;
and
a conducting line connected to the first and second groups of diffusion connections for each column.

8 more elements

Dependencies are inferred from the claim text.