Thin film transistor and fabricating method thereof an insulating layer having a pattern not being in contact with source or drain electrode
AssigneeLG.Philips LCD Co., Ltd.
InventorYong Min Ha
Life of this patent
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Abstract
The present invention relates to a thin film transistor and a fabricating method thereof which is applied to a buried bus coplanar type TFT wherein the source and drain wires are located on a substrate. The present invention includes an insulated substrate, a source electrode and a drain electrode on the insulated substrate, a first insulating layer on the insulated substrate wherein the first insulating layer has a predetermined pattern, an active layer on the first insulating layer wherein the active layer has a source region, a channel region and a drain region, a second insulating layer covering the active layer, and a gate electrode on the second insulating layer over the channel region.
Claims17
A thin film transistor comprising:
- a substrate;
- a source electrode and a drain electrode on the substrate;
- a first insulating layer on the substrate, the first insulating layer having a predetermined pattern such that the first insulating layer is not in contact with either the source electrode or the drain electrode;
- an active layer on the first insulating layer, the active layer having a source region, a channel region and a drain region;
- a second insulating layer covering the active layer;
- a gate electrode on the second insulating layer over the channel region;
- a third insulating layer covering the gate electrode and an exposed surface of the substrate;
- contact holes exposing the source and drain electrodes and the source and drain regions;
- a first interconnection wire connecting the source electrode to the source region;
- and
- a second interconnection wire connecting the drain electrode to the drain region,
- wherein the contact holes are substantially the same height.
A liquid crystal display comprising:
- a substrate;
- a data line on the substrate, the data line having a source electrode;
- a first insulating layer on the substrate, the first insulating layer having a predetermined pattern such that a first portion is formed, the first portion not being in contact with other portions of the first insulating layer, the first portion not being in contact with the source electrode;
- an active layer on the first insulating layer, the active layer having a source region, a channel region and a drain region;
- a second insulating layer covering an exposed surface of the substrate including the active layer and the data line;
- a gate line on the second insulating layer over the channel region, the gate line and the data line crossing each other, the gate line having a gate electrode;
- a third insulating layer on an exposed surface of the substrate including the gate line;
- contact holes exposing the source electrode, the source region and the drain region;
- an interconnection wire connecting the source electrode to the source region;
- and
- a pixel electrode connected to the drain region,
- wherein the contact holes are substantially the same height.
Dependencies are inferred from the claim text.