Single deposition layer metal dynamic random access memory

A memory device die, comprising:

• a plurality of memory sections, wherein each memory section includes a plurality of memory subarrays;
• a plurality of pitch cells connected to the plurality of memory sections;
• a plurality of power connections electrically connected to the plurality of pitch cells and the plurality of memory sections;
• an interior bonding pad formed between two of the plurality of memory sections, wherein the interior bonding pad is electrically connected to one or more of the plurality of memory sections;
• wherein the memory device die has at least 224 single-bit memory cells including only a single deposition layer of highly conductive interconnect material and one or more interconnect layers of non-highly conductive interconnect materia;
• and
• wherein the one or more interconnect layers of non-highly conductive interconnect materials is at least partially comprised of polysilicon interconnect.

A memory device, comprising:

• a memory device die, wherein the memory device die includes:
• a plurality of memory sections, wherein each memory section includes a plurality of memo subarrays;
• a plurality of pitch cells connected to the plurality of memory sections;
• a plurality of die-based power connections electrically connected to the plurality of pitch cells and the plurality of memory sections;
• and
• an interior bonding pad formed between two of the plurality of memory sections, wherein the interior bonding pad is electrically connected to one or more of the plurality of memory sections;
• a package for encasing the memory device die, wherein the package includes a plurality of power connections;
• a conductor, wherein the conductor is electrically connected to the interior bonding pad and to one of the plurality of power connections;
• and
• wherein the plurality of memory sections has a combined total of at least 224 single-bit memory cells.

A memory device, comprising:

• a memory device die, wherein the memory device die includes:
• a plurality of memory sections, wherein each memory section includes a plurality of memory subarrays;
• a plurality of pitch cells connected to the plurality of memory sections;
• a plurality of die-based power connections electrically connected to the plurality of pitch cells and the plurality of memory sections;
• and
• an interior bonding pad formed between two of the plurality of memory sections, wherein the interior bonding pad is electrically connected to one or more of the plurality of memory sections;
• a package for encasing the memory device die, wherein the package includes a plurality of power connections;
• and
• a conductor, wherein the conductor is electrically connected to the interior bonding pad and to one of the plurality of power connections;
• wherein the plurality of memory sections has a combined total of at least 224 single-bit memory cells;
• and
• wherein the memory device die is sized to fit within an industry standard package, the package having a maximum width of approximately 300 mils and a maximum length of approximately 675 mils.

A memory device, comprising:

• a memory device die, wherein the memory device die includes:
• a plurality of memory sections, wherein each memory section includes a plurality of memory subarrays;
• a plurality of pitch cells connected to the plurality of memory sections;
• a plurality of die-based power connections electrically connected to the plurality of pitch cells and the plurality of memory sections;
• and
• an interior bonding pad formed between two of the plurality of memory sections, wherein the interior bonding pad is electrically connected to one or more of the plurality of memory sections;
• a package for encasing the memory device die, wherein the package includes a plurality of power connections;
• and
• a conductor, wherein the conductor is electrically connected to the interior bonding pad and to one of the plurality of power connections;
• wherein the plurality of memory sections has a combined total of at least 224 single-bit memory cells;
• and
• wherein power and signal connections consist essentially of a single deposition layer of highly conductive interconnect material and at least one layer of non-highly conductive interconnect material.

A memory, comprising:

• a substrate;
• a multi-layer assembly formed on the substrate and having at least at least 224 single-bit memory cells, an address system and bonding pads;
• an interconnect assembly configured to facilitate data and power communication between the memory cells, address system and bonding pads, the interconnect assembly consisting of at least one dielectric layer, at least one semiconductor layer, and only one highly conductive layer;
• and
• an interior bonding pad formed in an interior area of the memory device, wherein the interior bonding pad is electrically connected to the interconnect assembly.

A memory, comprising:

• a substrate;
• a multi-layer assembly formed on the substrate and having at least at least 224 single-bit memory cells, an address system and bonding pads;
• an interconnect assembly configured to facilitate data and power communication between the memory cells, address system and bonding pads, the interconnect assembly consisting of at least one dielectric layer, at least one semiconductor layer, and only one highly conductive layer;
• an interior bonding pad formed in an interior area of the memory device, wherein the interior bonding pad is electrically connected to the interconnect assembly;
• wherein the plurality of the subarrays contain no more than 218 single bit memory cells;
• and
• wherein a plurality of word lines across one of the plurality of subarrays are a part of the semiconductor layer of the interconnect assembly which interconnects portions of a plurality of row address decoders to the single-bit memory cells.

A memory, comprising:

• a substrate;
• a multi-layer assembly formed on the substrate and having at least at least 224 single-bit memory cells, an address system and bonding pads;
• an interconnect assembly configured to facilitate data and power communication between the memory cells, address system and bonding pads, the interconnect assembly consisting of at least one dielectric layer, at least one semiconductor layer, and only one highly conductive layer;
• an interior bonding pad formed in an interior area of the memory device, wherein the interior bonding pad is electrically connected to the interconnect assembly;
• wherein the plurality of the subarrays contain no more than 218 single bit memory cells;
• and
• wherein a plurality of bit lines across the subarray are a part of the highly conductive layer which interconnects other portions of the plurality of column address decoders and sense amplifiers to the single-bit memory cells.

A memory, comprising:

• a substrate;
• a multi-layer assembly formed on the substrate and having at least at least 224 single-bit memory cells, an address system and bonding pads;
• an interconnect assembly configured to facilitate data and power communication between the memory cells, address system and bonding pads, the interconnect assembly consisting of at least one dielectric layer, at least one semiconductor layer, and only one highly conductive layer;
• an interior bonding pad formed in an interior area of the memory device, wherein the interior bonding pad is electrically connected to the interconnect assembly;
• and
• wherein the memory is configured to fit within an industry standard package which conforms to the JEDEC R-PDSO-J standard for Small Outline J-wing (SOJ) packaging.

A memory, comprising:

• a substrate;
• a multi-layer assembly formed on the substrate and having at least at least 224 single-bit memory cells, an address system and bonding pads;
• an interconnect assembly configured to facilitate data and power communication between the memory cells, address system and bonding pads, the interconnect assembly consisting of at least one dielectric layer, at least one semiconductor layer, and only one highly conductive layer;
• an interior bonding pad formed in an interior area of the memory device, wherein the interior bonding pad is electrically connected to the interconnect assembly;
• and
• wherein the memory is configured to fit within an industry standard package which conforms to the JEDEC R-PDSO-J standard for Thin, Small Outline Packaging (TSOP).

A memory, comprising:

• a substrate;
• a multi-layer assembly formed on the substrate and having at least at least 224 single-bit memory cells, an address system and bonding pads;
• an interconnect assembly configured to facilitate data and power communication between the memory cells, address system and bonding pads, the interconnect assembly consisting of at least one dielectric layer, at least one semiconductor layer, and only one highly conductive layer;
• an interior bonding pad formed in an interior area of the memory device, wherein the interior bonding pad is electrically connected to the interconnect assembly;
• and
• wherein features of the memory have a 0.5 micron or smaller minimum width of a smallest feature.

A dynamic random access memory part, comprising:

• a package having an outline approximately 300 mils wide and 675 mils long and having a cavity;
• a semiconductor die sized to fit within the cavity in the package and further comprising:
• a plurality of memory cells having at least 224 single-bit memory locations;
• a plurality of I/O bonding pads placed around the periphery of the die, a plurality of first power bonding pads placed around the periphery of the die, and a plurality of second power bonding pads placed in the interior of the die;
• a plurality of pitch cells fabricated to address, read and write the plurality of memory cells;
• an interconnect assembly configured to facilitate data and power communication between the memory cells, the I/O bonding pads, the first and second power bonding pads, and the pitch cells, the interconnect assembly consisting of at least one dielectric layer, at least one polysilicon layer, and only one highly conductive layer, and
• a lead frame attached to the package and placed over the semiconductor die and wire bonded to electrically connect the lead frame to the plurality of I/O bonding pads and to the plurality of first and second power bonding pads.

A dynamic random access memory part comprising:

• an industry standard JEDEC package having an outline approximately 340 mils wide and approximately 670 mils long and having a centrally located interior cavity;
• the semiconductor die sized to fit within the interior cavity of the package and further comprising:
• a plurality of memory cells having at least 224 single-bit addressable memory locations arranged as physical arrays, each of the physical arrays having no more than 218 single-bit addressable memory locations;
• a plurality of signal bonding pads placed around the periphery of the die, a plurality of power bonding pads placed around the periphery of the die, and a plurality of power bonding pads placed in the interior of the die;
• an interconnect assembly consisting essentially of:
• no more than one metal interconnect layer fabricated for connecting portions of the peripheral signal bonding pads to row address decoders and column address decoders, portions of bit lines connecting the plurality of the memory cells to sense amplifiers, and the peripheral power bonding pads and interior power bonding pads on the semiconductor die to the row address decoders, the column address decoders and the sense amplifiers;
• and
• at least one polysilicon interconnect layer for connecting portions of the memory cells, the signal bonding pads, the row address decoders, the column address decoders and the sense amplifiers.

A memory device, comprising:

• a lead assembly;
• and
• a die, comprising,
• at least 16 million memory cells;
• a first plurality of address lines, each line in contact with a first portion of said memory cells;
• a second plurality of address lines, each line in communication with a second portion of said memory cells, and
• a plurality of bondpads, said bondpads, said memory cells, and a selected one of said first and second plurality of address lines, each formed through an interconnect assembly consisting essentially of a single highly conductive layer and a semiconductor interconnect layer.