Method of improving MOS device performance by controlling degree of depletion in the gate electrode

A transistor comprising:

• a semiconductor substrate;
• a source region within said substrate;
• a drain region within said substrate, separated from said source region by a channel region within said substrate, wherein said channel region has an impurity concentration of between 1×1017 and 5×1018 atoms/cm3;
• an insulating layer formed on an upper surface of said channel region;
• and
• a conductive gate formed on said insulating layer, the conductive gate comprising amorphous silicon with an impurity concentration of between 1×1019 and 5×1019 atoms/cm3, wherein when said transistor is conducting, the degree of depletion of the conductive gate is greater than a minimum degree of depletion.

A method of fabricating a transistor device comprising:

• providing a semiconductor substrate;
• doping said substrate to prepare a channel region having a dopant concentration of between 1×1017 and 5×1018 atoms/cm3;
• forming an insulating layer on a top surface of said semiconductor substrate adjacent said channel region;
• forming a layer of polysilicon on said insulating layer;
• patterning said polysilicon layer and said insulating layer to form a polysilicon gate and exposed surfaces of said substrate;
• implanting an impurity species into said exposed surfaces and said polysilicon gate simultaneously, wherein the concentration of impurity species in said polysilicon gate is between 1×1019 and 5×109 atoms/cm3 such that an increase in said impurity concentration changes the electrical properties of said polysilicon.