US 6,274,914 B1Granted

CMOS integrated circuits including source/drain plug

AssigneeSamsung Electronics Co., Ltd.

InventorsYoung-hoon Park, Yang-koo Lee, Kyung-seok Oh

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Abstract

A CMOS integrated circuit includes an NMOS transistor and a PMOS transistor in an integrated circuit substrate. The NMOS transistor and the PMOS transistor each include a gate, and a source/drain on opposing sides of the gate. An insulating layer is located on the integrated circuit substrate. The insulating layer includes a contact hole therein which exposes a portion of a corresponding one of the source/drains. A source/drain plug is formed in the corresponding one of the source/drains. The source/drain plug is of opposite conductivity from the corresponding one of the source/drains. The source/drain plug is centered about the portion of the corresponding one of the source/drains. The source/drain plug may be formed by ion implantation through the contact hole and is thereby self-aligned to the contact hole. The source/drain plug can compensate for misalignment and the diffusion for highly integrated CMOS devices.

Claims24

Dependent claims

A CMOS integrated circuit comprising:

an integrated circuit substrate;
an NMOS transistor and a PMOS transistor in the integrated circuit substrate, the NMOS transistor and the PMOS transistor each including a gate, and a source/drain on opposing sides of the gate;
an insulating layer on the integrated circuit substrate, the insulating layer including a first contact hole therein, the first contact hole exposing a portion of a first one of the source/drains, the insulating layer also including a second contact hole therein, the second contact hole exposing a portion of a second one of the source/drains of opposite conductivity type from the first one of the source/drains;
a first source/drain plug in the first one of the source/drains, of opposite conductivity type from the first one of the source/drains and located in the first one of the source/drains so as to shield the first one of the source/drains from an adjacent well in the integrated circuit substrate, which contains the second one of the source/drains and which is of same conductivity type as the first one of the source/drains;
a first wiring layer in the contact hole, electrically connected to the first source/drain plug;
and
a second wiring layer in the second contact hole, electrically connected to the second one of the source/drains.

4 more elements

A CMOS integrated circuit comprising:

an integrated circuit substrate;
an NMOS transistor and a PMOS transistor in the integrated circuit substrate, the NMOS transistor and the PMOS transistor each including a gate, and a source/drain on opposing sides of the gate;
an insulating layer on the integrated circuit substrate, the insulating layer including a first contact hole therein, the first contact hole exposing a portion of a first one of the source/drains, the insulating layer also including a second contact hole therein, the second contact hole exposing a portion of a second one of the source/drains of opposite conductivity type from the first one of the source/drains;
a first source/drain plug in the first one of the source/drains, of opposite conductivity from the first one of the source/drains and located in the first one of the source/drains so as to shield the first one of the source/drains from an adjacent well in the integrated circuit substrate, which contains the second one of the source/drains and which is of same conductivity type as the first one of the source/drains;
a first wiring layer in the contact hole electrically connected to the first source/drain plug;
a second source/drain plug in the second one of the source/drains, of same conductivity type as the second one of the source/drains;
and
a second wiring layer in the second contact hole, electrically connected to the second source/drain plug.

5 more elements

A CMOS integrated circuit comprising:

an integrated circuit substrate;
an NMOS transistor and a PMOS transistor in the integrated circuit substrate, the NMOS transistor and the PMOS transistor each including a gate, and a source/drain on opposing sides of the gate;
an insulating layer on the integrated circuit substrate, the insulating layer including a first contact hole therein, the first contact hole exposing a portion of a first one of the source/drains, the insulating layer also including a second contact hole therein, the second contact hole exposing a portion of a second one of the source/drains of opposite conductivity type from the first one of the source/drains;
a first source/drain plug in the first one of the source/drains, of opposite conductivity type from the first one of the source/drains and located in the first one of the source/drains so as to shield the first one of the source/drains from an adjacent well in the integrated circuit substrate, which contains the second one of the source/drains and which is of same conductivity type as the first one of the source/drains;
a first wiring layer in the contact hole, electrically connected to the first source/drain plug;
a second source/drain plug in the second one of the source/drains, of opposite conductivity type from the second one of the source/drains;
and
a second wiring layer in the second contact hole, electrically connected to the second source/drain plug.

5 more elements

Dependencies are inferred from the claim text.