US 6,274,912 B1 · Semiconductor memory cell and method of manufacturing the same

A semiconductor memory cell comprising a first transistor of a first conductivity type for read-out, a second transistor of a second conductivity type for write-in and a junction-field-effect transistor of the first conductivity type for current control,

said semiconductor memory cell having;
(1) a first semi-conductive region of the first conductivity type,
(2) a second semi-conductive or conductive region formed in a surface region of the first region, said second region forming a rectifier junction together with the first region,
(3) a third semi-conductive region of the second conductivity type formed in a surface region of the first region and spaced from the second region,
(4) a fourth semi-conductive region of the first conductivity type formed in a surface region of the third region,
(5) a fifth semi-conductive or conductive region formed in a surface region of the fourth region, said fifth region forming a rectifier junction together with the fourth region, and
(6) a gate portion shared by the first transistor and the second transistor, and formed on a barrier layer so as to bridge the first region and the fourth region and so as to bridge the second region and the third region,
wherein;
(A-1) one source/drain region of the first transistor is constituted of the surface region of the fourth region,
(A-2) the other source/drain region of the first transistor is constituted of the surface region of the first region sandwiched by the second region and the third region,
(A-3) a channel forming region of the first transistor is constituted of the surface region of the third region sandwiched by the surface region of the first region and the surface region of the fourth region,
(B-1) one source/drain region of the second transistor is constituted of the second region,
(B-2) the other source/drain region of the second transistor is constituted of the surface region of the third region constituting the channel forming region of the first transistor,
(B-3) a channel forming region of the second transistor is constituted of the surface region of the first region constituting the other source/drain region of the first transistor,
(C-1) gate regions of the junction-field-effect transistor are constituted of the fifth region and a portion of the third region facing the fifth region,
(C-2) a channel region of the junction-field-effect transistor is constituted of part of the fourth region sandwiched by the fifth region and said portion of the third region,
(C-3) one source/drain region of the junction-field-effect transistor is constituted of a portion of the fourth region extending from one end of the channel region of the junction-field-effect transistor and constituting one source/drain region of the first transistor,
(C-4) the other source/drain region of the junction-field-effect transistor is constituted of a portion of the fourth region extending from the other end of the channel region of the junction-field-effect transistor,
(D) the gate portion is connected to a first memory-cell-selecting line,
(E) a diode is formed between the first region and the second region, and the first region is connected to a write-in information setting line through the diode,
(F) the second region is connected to the write-in information setting line,
(G) the portion of the fourth region constituting the other source/drain region of the junction-field-effect transistor is connected to a second memory-cell-selecting line, and
(H) the fifth region is connected to a predetermined potential line.

20 more elements

A semiconductor memory cell comprising a first transistor of a first conductivity type for read-out, a second transistor of a second conductivity type for write-in, a junction-field-effect transistor of the first conductivity type for current control and a third transistor of the second conductivity type for write-in,

said semiconductor memory cell having;
(1) a first semi-conductive region of the first conductivity type,
(2) a second semi-conductive or conductive region formed in a surface region of the first region, said second region forming a rectifier junction together with the first region,
(3) a third semi-conductive region of the second conductivity type formed in a surface region of the first region and spaced from the second region,
(4) a fourth semi-conductive region of the first conductivity type formed in a surface region of the third region,
(5) a fifth semi-conductive or conductive region formed in a surface region of the fourth region, said fifth region forming a rectifier junction together with the fourth region, and
(6) a gate portion shared by the first transistor, the second transistor and the third transistor, and formed on a barrier layer so as to bridge the first region and the fourth region, so as to bridge the second region and the third region and so as to bridge the third region and the fifth region,
wherein;
(A-1) one source/drain region of the first transistor is constituted of the surface region of the fourth region,
(A-2) the other source/drain region of the first transistor is constituted of the surface region of the first region sandwiched by the second region and the third region,
(A-3) a channel forming region of the first transistor is constituted of the surface region of the third region sandwiched by the surface region of the first region and the surface region of the fourth region,
(B-1) one source/drain region of the second transistor is constituted of the second region,
(B-2) the other source/drain region of the second transistor is constituted of the surface region of the third region constituting the channel forming region of the first transistor,
(B-3) a channel forming region of the second transistor is constituted of the surface region of the first region constituting the other source/drain region of the first transistor,
(C-1) gate regions of the junction-field-effect transistor are constituted of the fifth region and a portion of the third region facing the fifth region,
(C-2) a channel region of the junction-field-effect transistor is constituted of part of the fourth region sandwiched by the fifth region and said portion of the third region,
(C-3) one source/drain region of the junction-field-effect transistor is constituted of a portion of the fourth region extending from one end of the channel region of the junction-field-effect transistor and constituting one source/drain region of the first transistor,
(C-4) the other source/drain region of the junction-field-effect transistor is constituted of a portion of the fourth region extending from the other end of the channel region of the junction-field-effect transistor,
(D-1) one source/drain region of the third transistor is constituted of the surface region of the third region constituting the channel forming region of the first transistor,
(D-2) the other source/drain region of the third transistor is constituted of the fifth region,
(D-3) a channel forming region of the third transistor is constituted of the surface region of the fourth region functioning as one source/drain region of the first transistor,
(E) the gate portion is connected to a first memory-cell-selecting line,
(F) a diode is formed between the first region and the second region, and the first region is connected to a write-in information setting line through the diode,
(G) the second region is connected to the write-in information setting line, and
(H) the portion of the fourth region constituting the other source/drain region of the junction-field-effect transistor is connected to a second memory-cell-selecting line.

22 more elements

A semiconductor memory cell comprising a first transistor of a first conductivity type for read-out, a second transistor of a second conductivity type for write-in and a junction-field-effect transistor of the first conductivity type for current control,

said semiconductor memory cell having;
(1) a first semi-conductive region of the first conductivity type,
(2) a second semi-conductive or conductive region formed in a surface region of the first region, said second region forming a rectifier junction together with the first region,
(3) a third semi-conductive region of the second conductivity type formed in a surface region of the first region and spaced from the second region,
(4) a fourth semi-conductive region of the first conductivity type formed in a surface region of the third region,
(5) a fifth semi-conductive or conductive region formed in a surface region of the fourth region, said fifth region forming a rectifier junction together with the fourth region, and
(6) a gate portion shared by the first transistor and the second transistor, and formed on a barrier layer so as to bridge the first region and the fourth region and so as to bridge the second region and the third region,
wherein;
(A-1) one source/drain region of the first transistor is constituted of the surface region of the fourth region,
(A-2) the other source/drain region of the first transistor is constituted of the surface region of the first region sandwiched by the second region and the third region,
(A-3) a channel forming region of the first transistor is constituted of the surface region of the third region sandwiched by the surface region of the first region and the surface region of the fourth region,
(B-1) one source/drain region of the second transistor is constituted of the second region,
(B-2) the other source/drain region of the second transistor is constituted of the surface region of the third region constituting the channel forming region of the first transistor,
(B-3) a channel forming region of the second transistor is constituted of the surface region of the first region constituting the other source/drain region of the first transistor,
(C-1) gate regions of the junction-field-effect transistor are constituted of the fifth region and a portion of the third region facing the fifth region,
(C-2) a channel region of the junction-field-effect transistor is constituted of part of the fourth region sandwiched by the fifth region and said portion of the third region,
(C-3) one source/drain region of the junction-field-effect transistor is constituted of a portion of the fourth region extending from one end of the channel region of the junction-field-effect transistor and constituting one source/drain region of the first transistor,
(C-4) the other source/drain region of the junction-field-effect transistor is constituted of a portion of the fourth region extending from the other end of the channel region of the junction-field-effect transistor,
(D) the gate portion is connected to a first memory-cell-selecting line,
(E) a diode is formed between the first region and the second region, and the first region is connected to a write-in information setting line through the diode,
(F) the second region and the fifth region are connected to the write-in information setting line, and
(G) the portion of the fourth region constituting the other source/drain region of the junction-field-effect transistor is connected to a predetermined potential line.

19 more elements

A semiconductor memory cell comprising a first transistor of a first conductivity type for read-out, a second transistor of a second conductivity type for write-in, a junction-field-effect transistor of the first conductivity type for current control and a third transistor of the second conductivity type for write-in,

said semiconductor memory cell having;
(1) a first semi-conductive region of the first conductivity type,
(2) a second semi-conductive or conductive region formed in a surface region of the first region, said second region forming a rectifier junction together with the first region,
(3) a third semi-conductive region of the second conductivity type formed in a surface region of the first region and spaced from the second region,
(4) a fourth semi-conductive region of the first conductivity type formed in a surface region of the third region,
(5) a fifth semi-conductive or conductive region formed in a surface region of the fourth region, said fifth region forming a rectifier junction together with the fourth region, and
(6) a gate portion shared by the first transistor, the second transistor and the third transistor, and formed on a barrier layer so as to bridge the first region and the fourth region, so as to bridge the second region and the third region and so as to bridge the third region and the fifth region,
wherein;
(A-1) one source/drain region of the first transistor is constituted of the surface region of the fourth region,
(A-2) the other source/drain region of the first transistor is constituted of the surface region of the first region sandwiched by the second region and the third region,
(A-3) a channel forming region of the first transistor is constituted of the surface region of the third region sandwiched by the surface region of the first region and the surface region of the fourth region,
(B-1) one source/drain region of the second transistor is constituted of the second region,
(B-2) the other source/drain region of the second transistor is constituted of the surface region of the third region constituting the channel forming region of the first transistor,
(B-3) a channel forming region of the second transistor is constituted of the surface region of the first region constituting the other source/drain region of the first transistor,
(C-1) gate regions of the junction-field-effect transistor are constituted of the fifth region and a portion of the third region facing the fifth region,
(C-2) a channel region of the junction-field-effect transistor is constituted of part of the fourth region sandwiched by the fifth region and the portion of the third region,
(C-3) one source/drain region of the junction-field-effect transistor is constituted of a portion of the fourth region extending from one end of the channel region of the junction-field-effect transistor and constituting one source/drain region of the first transistor,
(C-4) the other source/drain region of the junction-field-effect transistor is constituted of a portion of the fourth region extending from the other end of the channel region of the junction-field-effect transistor,
(D-1) one source/drain region of the third transistor is constituted of the surface region of the third region constituting the channel forming region of the first transistor,
(D-2) the other source/drain region of the third transistor is constituted of the fifth region,
(D-3) a channel forming region of the third transistor is constituted of the surface region of the fourth region functioning as one source/drain region of the first transistor,
(E) the gate portion is connected to a first memory-cell-selecting line,
(F) a diode is formed between the first region and the second region, and the first region is connected to a write-in information setting line through the diode,
(G) the second region is connected to the write-in information setting line, and
(H) the portion of the fourth region constituting the other source/drain region of the junction-field-effect transistor is connected to a predetermined potential line.

22 more elements

A method for manufacturing a semiconductor memory cell comprising at least a first transistor of a first conductivity type for read-out, a second transistor of a second conductivity type for write-in and a junction-field-effect transistor of the first conductivity type for current control,

said semiconductor memory cell having;
(1) a first semi-conductive region of the first conductivity type,
(2) a second semi-conductive or conductive region formed in a surface region of the first region, said second region forming a rectifier junction together with the first region,
(3) a third semi-conductive region of the second conductivity type formed in a surface region of the first region and spaced from the second region,
(4) a fourth semi-conductive region of the first conductivity type formed in a surface region of the third region,
(5) a fifth semi-conductive or conductive region formed in a surface region of the fourth region, said fifth region forming a rectifier junction together with the fourth region, and
(6) a gate portion shared by the first transistor and the second transistor, and formed on a barrier layer at least so as to bridge the first region and the fourth region and so as to bridge the second region and the third region,
the first transistor having;
(A-1) one source/drain region constituted of the surface region of the fourth region,
(A-2) the other source/drain region constituted of the surface region of the first region sandwiched by the second region and the third region, and
(A-3) a channel forming region constituted of the surface region of the third region sandwiched by the surface region of the first region and the surface region of the fourth region,
the second transistor having;
(B-1) one source/drain region constituted of the second region,
(B-2) the other source/drain region constituted of the surface region of the third region constituting the channel forming region of the first transistor, and
(B-3) a channel forming region constituted of the surface region of the first region constituting the other source/drain region of the first transistor, and
the junction-field-effect transistor having;
(C-1) gate regions constituted of the fifth region and a portion of the third region facing the fifth region,
(C-2) a channel region constituted of part of the fourth region sandwiched by the fifth region and said portion of the third region,
(C-3) one source/drain region constituted of a portion of the fourth region extending from one end of the channel region of the junction-field-effect transistor and constituting one source/drain region of the first transistor,
(C-4) the other source/drain region constituted of a portion of the fourth region extending from the other end of the channel region of the junction-field-effect transistor,
said method comprising the steps of;
forming the barrier layer at least on the surfaces of the first region and the third region, and then, forming the gate portion on the barrier layer, and
forming the third region, the fourth region and the fifth region by ion implantation in an arbitrary order so as to optimize a distance between the facing gate regions of the junction-field-effect transistor and so as to optimize impurity concentrations of the facing gate regions and the channel region of the junction-field-effect transistor.

20 more elements

A semiconductor memory cell provided with a semi-conductive layer having a first main surface and a second main surface opposed to the first main surface, said semiconductor memory cell comprising a first transistor of a first conductivity type for read-out, a second transistor of a second conductivity type for write-in and a junction-field-effect transistor of the first conductivity type for current control, and having;

(1) a first semi-conductive region of the first conductivity type, formed through the semi-conductive layer from the first main surface to the second main surface,
(2) a second semi-conductive region of the second conductivity type, formed through the semi-conductive layer from the first main surface to the second main surface and being in contact with the first region,
(3) a third semi-conductive or conductive region formed in a surface region, including the second main surface, of the first region and spaced from the second region, said third region forming a rectifier junction together with the first region,
(4) a fourth semi-conductive or conductive region formed in a surface region, including the first main surface, of the second region and spaced from the first region, said fourth region forming a rectifier junction together with the second region,
(5) a fifth semi-conductive or conductive region formed in a surface region, including the first main surface, of the first region and spaced from the second region, said fifth region forming a rectifier junction together with the first region,
(6) a gate portion of the first transistor formed on a barrier layer formed on the first main surface so as to bridge the first region and the fourth region, and
(7) a gate portion of the second transistor formed on a barrier layer formed on the second main surface so as to bridge the second region and the third region,
wherein;
(A-1) one source/drain region of the first transistor is constituted of a surface region, including the first main surface, of the first region,
(A-2) the other source/drain region of the first transistor is constituted of the fourth region,
(A-3) a channel forming region of the first transistor is constituted of a surface region, including the first main surface, of the second region which surface region is sandwiched by the surface region, including the first main surface, of the first region and the fourth region,
(B-1) one source/drain region of the second transistor is constituted of the third region,
(B-2) the other source/drain region of the second transistor is constituted of a surface region, including the second main surface, of the second region,
(B-3) a channel forming region of the second transistor is constituted of a surface region, including the second main surface, of the first region which surface region is sandwiched by the third region and the surface region, including the second main surface, of the second region,
(C-1) gate regions of the junction-field-effect transistor are constituted of the fifth region and the third region facing the fifth region,
(C-2) a channel region of the junction-field-effect transistor is constituted of a portion of the first region sandwiched by the fifth region and the third region,
(C-3) one source/drain region of the junction-field-effect transistor is constituted of a portion of the first region extending from one end of the channel region of the junction-field-effect transistor and constituting one source/drain region of the first transistor and the channel forming region of the second transistor,
(C-4) the other source/drain region of the junction-field-effect transistor is constituted of a portion of the first region extending from the other end of the channel region of the junction-field-effect transistor,
(D) the gate portion of the first transistor and the gate portion of the second transistor are connected to a first memory-cell-selecting line,
(E) the third region is connected to a write-in information setting line,
(F) the fourth region is connected to a second memory-cell-selecting line,
(G) the other source/drain region of the junction-field-effect transistor is connected to a predetermined potential line, and
(H) the fifth region is connected to a second predetermined potential line.

20 more elements

A semiconductor memory cell provided with a semi-conductive layer having a first main surface and a second main surface opposed to the first main surface, said semiconductor memory cell comprising a first transistor of a first conductivity type for read-out, a second transistor of a second conductivity type for write-in and a junction-field-effect transistor of the first conductivity type for current control, and having;

(1) a first semi-conductive region of the first conductivity type, formed through the semi-conductive layer from the first main surface to the second main surface,
(2) a second semi-conductive region of the second conductivity type, formed through the semi-conductive layer from the first main surface to the second main surface and being in contact with the first region,
(3) a third semi-conductive or conductive region formed in a surface region, including the second main surface, of the first region and spaced from the second region, said third region forming a rectifier junction together with the first region,
(4) a fourth semi-conductive or conductive region formed in a surface region, including the first main surface, of the second region and spaced from the first region, said fourth region forming a rectifier junction together with the second region,
(5) a fifth semi-conductive or conductive region formed in a surface region of the fourth region, said fifth region forming a rectifier junction together with the fourth region,
(6) a gate portion of the first transistor formed on a barrier layer formed on the first main surface so as to bridge the first region and the fourth region, and
(7) a gate portion of the second transistor formed on a barrier layer formed on the second main surface so as to bridge the second region and the third region,
wherein;
(A-1) one source/drain region of the first transistor is constituted of a surface region, including the first main surface, of the first region,
(A-2) the other source/drain region of the first transistor is constituted of the fourth region,
(A-3) a channel forming region of the first transistor is constituted of a surface region, including the first main surface, of the second region which surface region is sandwiched by the surface region, including the first main surface, of the first region and the fourth region,
(B-1) one source/drain region of the second transistor is constituted of the third region,
(B-2) the other source/drain region of the second transistor is constituted of a surface region, including the second main surface, of the second region,
(B-3) a channel forming region of the second transistor is constituted of a surface region, including the second main surface, of the first region which surface region is sandwiched by the third region and the surface region, including the second main surface, of the second region,
(C-1) gate regions of the junction-field-effect transistor are constituted of the fifth region and a portion of the second region facing the fifth region,
(C-2) a channel region of the junction-field-effect transistor is constituted of a portion of the fourth region sandwiched by the fifth region and said portion of the second region,
(C-3) one source/drain region of the junction-field-effect transistor is constituted of a portion of the fourth region extending from one end of the channel region of the junction-field-effect transistor and constituting the other source/drain region of the first transistor,
(C-4) the other source/drain region of the junction-field-effect transistor is constituted of a portion of the fourth region extending from the other end of the channel region of the junction-field-effect transistor,
(D) the gate portion of the first transistor and the gate portion of the second transistor are connected to a first memory-cell-selecting line,
(E) the third region is connected to a write-in information setting line,
(F) the first region is connected to a predetermined potential line,
(G) the other source/drain region of the junction-field-effect transistor is connected to a second memory-cell-selecting line, and
(H) the fifth region is connected to a second predetermined potential line.

20 more elements

A semiconductor memory cell provided with a semi-conductive layer having a first main surface and a second main surface opposed to the first main surface, said semiconductor memory cell comprising a first transistor of a first conductivity type for read-out, a second transistor of a second conductivity type for write-in, a first junction-field-effect transistor of the first conductivity type for current control and a second junction-field-effect transistor of the first conductivity type for current control, and having;

(1) a first semi-conductive region of the first conductivity type, formed through the semi-conductive layer from the first main surface to the second main surface,
(2) a second semi-conductive region of the second conductivity type, formed through the semi-conductive layer from the first main surface to the second main surface and being in contact with the first region,
(3) a third semi-conductive or conductive region formed in a surface region, including the second main surface, of the first region and spaced from the second region, said third region forming a rectifier junction together with the first region,
(4) a fourth semi-conductive or conductive region formed in a surface region, including the first main surface, of the second region and spaced from the first region, said fourth region forming a rectifier junction together with the second region,
(5) a fifth semi-conductive or conductive region formed in a surface region of the fourth region, said fifth region forming a rectifier junction together with the fourth region,
(6) a sixth semi-conductive or conductive region formed in a surface region, including the first main surface, of the first region and spaced from the second region, said sixth region forming a rectifier junction together with the first region,
(7) a gate portion of the first transistor formed on a barrier layer formed on the first main surface so as to bridge the first region and the fourth region, and
(8) a gate portion of the second transistor formed on a barrier layer formed on the second main surface so as to bridge the second region and the third region,
wherein;
(A-1) one source/drain region of the first transistor is constituted of a surface region, including the first main surface, of the first region,
(A-2) the other source/drain region of the first transistor is constituted of the fourth region,
(A-3) a channel forming region of the first transistor is constituted of a surface region, including the first main surface, of the second region which surface region is sandwiched by the surface region, including the first main surface, of the first region and the fourth region,
(B-1) one source/drain region of the second transistor is constituted of the third region,
(B-2) the other source/drain region of the second transistor is constituted of a surface region, including the second main surface, of the second region,
(B-3) a channel forming region of the second transistor is constituted of a surface region, including the second main surface, of the first region which surface region is sandwiched by the third region and the surface region, including the second main surface, of the second region,
(C-1) gate regions of the first junction-field-effect transistor are constituted of the fifth region and a portion of the second region facing the fifth region,
(C-2) a channel region of the first junction-field-effect transistor is constituted of a portion of the fourth region sandwiched by the fifth region and said portion of the second region,
(C-3) one source/drain region of the first junction-field-effect transistor is constituted of a portion of the fourth region extending from one end of the channel region of the first junction-field-effect transistor and constituting the other source/drain region of the first transistor,
(C-4) the other source/drain region of the first junction-field-effect transistor is constituted of a portion of the fourth region extending from the other end of the channel region of the first junction-field-effect transistor,
(D-1) gate regions of the second junction-field-effect transistor are constituted of the sixth region and the third region,
(D-2) a channel region of the second junction-field-effect transistor is constituted of a portion of the first region sandwiched by the sixth region and the third region,
(D-3) one source/drain region of the second junction-field-effect transistor is constituted of a portion of the first region extending from one end of the channel region of the second junction-field-effect transistor and constituting one source/drain region of the first transistor and the channel forming region of the second transistor,
(D-4) the other source/drain region of the second junction-field-effect transistor is constituted of a portion of the first region extending from the other end of the channel region of the second junction-field-effect transistor,
(E) the gate portion of the first transistor and the gate portion of the second transistor are connected to a first memory-cell-selecting line,
(F) the third region is connected to a write-in information setting line,
(G) the other source/drain region of the second junction-field-effect transistor is connected to a predetermined potential line,
(H) the other source/drain region of the first junction-field-effect transistor is connected to a second memory-cell-selecting line, and
(I) the fifth region and the sixth region are connected to a second predetermined potential line.

25 more elements

A semiconductor memory cell provided with a semi-conductive layer having a first main surface and a second main surface opposed to the first main surface, said semiconductor memory cell comprising a first transistor of a first conductivity type for read-out, a second transistor of a second conductivity type for write-in, a junction-field-effect transistor of the first conductivity type for current control and a third transistor of the second conductivity type for write-in, and having;

(1) a first semi-conductive region of the first conductivity type, formed through the semi-conductive layer from the first main surface to the second main surface,
(2) a second semi-conductive region of the second conductivity type, formed through the semi-conductive layer from the first main surface to the second main surface and being in contact with the first region,
(3) a third semi-conductive or conductive region formed in a surface region, including the second main surface, of the first region and spaced from the second region, said third region forming a rectifier junction together with the first region,
(4) a fourth semi-conductive or conductive region formed in a surface region, including the first main surface, of the second region and spaced from the first region, said fourth region forming a rectifier junction together with the second region,
(5) a fifth semi-conductive or conductive region formed in a surface region of the fourth region, said fifth region forming a rectifier junction together with the fourth region,
(6) a gate portion shared by the first transistor and the third transistor, and formed on a barrier layer formed on the first main surface so as to bridge the first region and the fourth region and so as to bridge the second region and the fifth region, and
(7) a gate portion of the second transistor formed on a barrier layer formed on the second main surface so as to bridge the second region and the third region,
wherein;
(A-1) one source/drain region of the first transistor is constituted of a surface region, including the first main surface, of the first region,
(A-2) the other source/drain region of the first transistor is constituted of the fourth region,
(A-3) a channel forming region of the first transistor is constituted of a surface region, including the first main surface, of the second region which surface region is sandwiched by the surface region, including the first main surface, of the first region and the fourth region,
(B-1) one source/drain region of the second transistor is constituted of the third region,
(B-2) the other source/drain region of the second transistor is constituted of a surface region, including the second main surface, of the second region,
(B-3) a channel forming region of the second transistor is constituted of a surface region, including the second main surface, of the first region which surface region is sandwiched by the third region and the surface region, including the second main surface, of the second region,
(C-1) gate regions of the junction-field-effect transistor are constituted of the fifth region and a portion of the second region facing the fifth region,
(C-2) a channel region of the junction-field-effect transistor is constituted of a portion of the fourth region sandwiched by the fifth region and said portion of the second region,
(C-3) one source/drain region of the junction-field-effect transistor is constituted of a portion of the fourth region extending from one end of the channel region of the junction-field-effect transistor and constituting the other source/drain region of the first transistor,
(C-4) the other source/drain region of the junction-field-effect transistor is constituted of a portion of the fourth region extending from the other end of the channel region of the junction-field-effect transistor,
(D-1) one source/drain region of the third transistor is constituted of the channel forming region of the first transistor,
(D-2) the other source/drain region of the third transistor is constituted of the fifth region,
(D-3) a channel forming region of the third transistor is constituted of the other source/drain region of the first transistor,
(E) the gate portion shared by the first transistor and the third transistor and the gate portion of the second transistor are connected to a first memory-cell-selecting line,
(F) the third region is connected to a write-in information setting line,
(G) the first region is connected to a predetermined potential line, and
(H) the other source/drain region of the junction-field-effect transistor is connected to a second memory-cell-selecting line.

22 more elements

A semiconductor memory cell provided with a semi-conductive layer having a first main surface and a second main surface opposed to the first main surface, said semiconductor memory cell comprising a first transistor of a first conductivity type for read-out, a second transistor of a second conductivity type for write-in, a first junction-field-effect transistor of the first conductivity type for current control, a second junction-field-effect transistor of the first conductivity type for current control and a third transistor of the second conductivity type for write-in, and having;

(1) a first semi-conductive region of the first conductivity type, formed through the semi-conductive layer from the first main surface to the second main surface,
(2) a second semi-conductive region of the second conductivity type, formed through the semi-conductive layer from the first main surface to the second main surface and being in contact with the first region,
(3) a third semi-conductive or conductive region formed in a surface region, including the second main surface, of the first region and spaced from the second region, said third region forming a rectifier junction together with the first region,
(4) a fourth semi-conductive or conductive region formed in a surface region, including the first main surface, of the second region and spaced from the first region, said fourth region forming a rectifier junction together with the second region,
(5) a fifth semi-conductive or conductive region formed in a surface region of the fourth region, said fifth region forming a rectifier junction together with the fourth region,
(6) a sixth semi-conductive or conductive region formed in a surface region, including the first main surface, of the first region and spaced from the second region, said sixth region forming a rectifier junction together with the first region,
(7) a gate portion shared by the first transistor and the third transistor, and formed on a barrier layer formed on the first main surface so as to bridge the first region and the fourth region and so as to bridge the second region and the fifth region, and
(8) a gate portion of the second transistor formed on a barrier layer formed on the second main surface so as to bridge the second region and the third region,
wherein;
(A-1) one source/drain region of the first transistor is constituted of a surface region, including the first main surface, of the first region,
(A-2) the other source/drain region of the first transistor is constituted of the fourth region,
(A-3) a channel forming region of the first transistor is constituted of a surface region, including the first main surface, of the second region which surface region is sandwiched by the surface region, including the first main surface, of the first region and the fourth region,
(B-1) one source/drain region of the second transistor is constituted of the third region,
(B-2) the other source/drain region of the second transistor is constituted of a surface region, including the second main surface, of the second region,
(B-3) a channel forming region of the second transistor is constituted of a surface region, including the second main surface, of the first region which surface region is sandwiched by the third region and the surface region, including the second main surface, of the second region,
(C-1) gate regions of the first junction-field-effect transistor are constituted of the fifth region and a portion of the second region facing the fifth region,
(C-2) a channel region of the first junction-field-effect transistor is constituted of a portion of the fourth region sandwiched by the fifth region and said portion of the second region,
(C-3) one source/drain region of the first junction-field-effect transistor is constituted of a portion of the fourth region extending from one end of the channel region of the first junction-field-effect transistor and constituting the other source/drain region of the first transistor,
(C-4) the other source/drain region of the first junction-field-effect transistor is constituted of a portion of the fourth region extending from the other end of the channel region of the first junction-field-effect transistor,
(D-1) gate regions of the second junction-field-effect transistor are constituted of the sixth region and the third region,
(D-2) a channel region of the second junction-field-effect transistor is constituted of a portion of the first region sandwiched by the sixth region and the third region,
(D-3) one source/drain region of the second junction-field-effect transistor is constituted of a portion of the first region extending from one end of the channel region of the second junction-field-effect transistor and constituting one source/drain region of the first transistor and the channel forming region of the second transistor,
(D-4) the other source/drain region of the second junction-field-effect transistor is constituted of a portion of the first region extending from the other end of the channel region of the second junction-field-effect transistor,
(E-1) one source/drain region of the third transistor is constituted of the channel forming region of the first transistor,
(E-2) the other source/drain region of the third transistor is constituted of the fifth region,
(E-3) a channel forming region of the third transistor is constituted of the other source/drain region of the first transistor,
(F) the gate portion shared by the first transistor and the third transistor and the gate portion of the second transistor are connected to a first memory-cell-selecting line,
(G) the third region is connected to a write-in information setting line,
(H) the other source/drain region of the second junction-field-effect transistor is connected to a predetermined potential line,
(I) the other source/drain region of the first junction-field-effect transistor is connected to a second memory-cell-selecting line, and
(J) the sixth region is connected to a second predetermined potential line.

28 more elements

A method for manufacturing a semiconductor memory cell provided with a semi-conductive layer having a first main surface and a second main surface opposed to the first main surface, said semiconductor memory cell comprising a first transistor of a first conductivity type for read-out, a second transistor of a second conductivity type for write-in and a junction-field-effect transistor of the first conductivity type for current control, and having;

(1) a first semi-conductive region of the first conductivity type, formed through the semi-conductive layer from the first main surface to the second main surface,
(2) a second semi-conductive region of the second conductivity type, formed through the semi-conductive layer from the first main surface to the second main surface and being in contact with the first region,
(3) a third semi-conductive or conductive region formed in a surface region, including the second main surface, of the first region and spaced from the second region, said third region forming a rectifier junction together with the first region,
(4) a fourth semi-conductive or conductive region formed in a surface region, including the first main surface, of the second region and spaced from the first region, said fourth region forming a rectifier junction together with the second region,
(5) a fifth semi-conductive or conductive region formed in a surface region, including the first main surface, of the first region and spaced from the second region, said fifth region forming a rectifier junction together with the first region,
(6) a gate portion of the first transistor formed on a barrier layer formed on the first main surface so as to bridge the first region and the fourth region, and
(7) a gate portion of the second transistor formed on a barrier layer formed on the second main surface so as to bridge the second region and the third region,
the first transistor having;
(A-1) one source/drain region constituted of a surface region, including the first main surface, of the first region,
(A-2) the other source/drain region constituted of the fourth region, and
(A-3) a channel forming region constituted of a surface region, including the first main surface, of the second region which surface region is sandwiched by the surface region, including the first main surface, of the first region and the fourth region,
the second transistor having;
(B-1) one source/drain region constituted of the third region,
(B-2) the other source/drain region constituted of a surface region, including the second main surface, of the second region, and
(B-3) a channel forming region constituted of a surface region, including the second main surface, of the first region which surface region is sandwiched by the third region and the surface region, including the second main surface, of the second region, and
the junction-field-effect transistor having;
(C-1) gate regions constituted of the fifth region and the third region facing the fifth region,
(C-2) a channel region constituted of a portion of the first region sandwiched by the fifth region and the third region,
(C-3) one source/drain region constituted of a portion of the first region extending from one end of the channel region of the junction-field-effect transistor and constituting one source/drain region of the first transistor and the channel forming region of the second transistor, and
(C-4) the other source/drain region constituted of a portion of the first region extending from the other end of the channel region of the junction-field-effect transistor,
said method comprising the steps of;
forming the barrier layer on the first main surface and then, forming the gate portion of the first transistor on the barrier layer, and forming the barrier layer on the second main surface and then, forming the gate portion of the second transistor on the barrier layer, and
forming the first region, the third region and the fifth region by ion implantation in an arbitrary order so as to optimize a distance between the facing gate regions of the junction-field-effect transistor and so as to optimize impurity concentrations of the facing gate regions and the channel region of the junction-field-effect transistor.

20 more elements

A method for manufacturing a semiconductor memory cell provided with a semi-conductive layer having a first main surface and a second main surface opposed to the first main surface, said semiconductor memory cell comprising at least a first transistor of a first conductivity type for read-out, a second transistor of a second conductivity type for write-in and a junction-field-effect transistor of the first conductivity type for current control, and having at least;

(1) a first semi-conductive region of the first conductivity type, formed through the semi-conductive layer from the first main surface to the second main surface,
(2) a second semi-conductive region of the second conductivity type, formed through the semi-conductive layer from the first main surface to the second main surface and being in contact with the first region,
(3) a third semi-conductive or conductive region formed in a surface region, including the second main surface, of the first region and spaced from the second region, said third region forming a rectifier junction together with the first region,
(4) a fourth semi-conductive or conductive region formed in a surface region, including the first main surface, of the second region and spaced from the first region, said fourth region forming a rectifier junction together with the second region,
(5) a fifth semi-conductive or conductive region formed in a surface region of the fourth region, said fifth region forming a rectifier junction together with the fourth region,
(6) a gate portion of the first transistor formed on a barrier layer formed on the first main surface so as to bridge the first region and the fourth region, and
(7) a gate portion of the second transistor formed on a barrier layer formed on the second main surface so as to bridge the second region and the third region,
the first transistor having;
(A-1) one source/drain region constituted of a surface region, including the first main surface, of the first region,
(A-2) the other source/drain region constituted of the fourth region, and
(A-3) a channel forming region constituted of a surface region, including the first main surface, of the second region which surface region is sandwiched by the surface region, including the first main surface, of the first region and the fourth region,
the second transistor having;
(B-1) one source/drain region constituted of the third region,
(B-2) the other source/drain region constituted of a surface region, including the second main surface, of the second region, and
(B-3) a channel forming region constituted of a surface region, including the second main surface, of the first region which surface region is sandwiched by the third region and the surface region, including the second main surface, of the second region, and
the junction-field-effect transistor having;
(C-1) gate regions constituted of the fifth region and a portion of the second region facing the fifth region,
(C-2) a channel region constituted of a portion of the fourth region sandwiched by the fifth region and said portion of the second region,
(C-3) one source/drain region constituted of a portion of the fourth region extending from one end of the channel region of the junction-field-effect transistor and constituting the other source/drain region of the first transistor, and
(C-4) the other source/drain region constituted of a portion of the fourth region extending from the other end of the channel region of the junction-field-effect transistor,
said method comprising the steps of;
forming the barrier layer on the first main surface and then, forming the gate portion of the first transistor on the barrier layer, and forming the barrier layer on the second main surface and then, forming the gate portion of the second transistor on the barrier layer, and
forming the second region, the fourth region and the fifth region by ion implantation in an arbitrary order so as to optimize a distance between the facing gate regions of the junction-field-effect transistor and so as to optimize impurity concentrations of the facing gate regions and the channel region of the junction-field-effect transistor.

20 more elements

A semiconductor memory cell comprising a first transistor of a first conductivity type for read-out, a second transistor of a second conductivity type for write-in and a diode,

said semiconductor memory cell having;
(1) a first semi-conductive region of the second conductivity type,
(2) a second semi-conductive or conductive region forming a rectifier junction together with the first region,
(3) a third semi-conductive region of the first conductivity type, in contact with the first region and spaced from the second region,
(4) a fourth semi-conductive or conductive region formed in a surface region of the third region, said fourth region forming a rectifier junction together with the third region, and
(5) a gate portion shared by the first transistor and the second transistor, and formed on a barrier layer so as to bridge the second region and the third region and so as to bridge the first region and the fourth region,
wherein;
(A-1) one source/drain region of the first transistor is constituted of the second region,
(A-2) the other source/drain region of the first transistor is constituted of the third region,
(A-3) a channel forming region of the first transistor is constituted of a surface region of the first region sandwiched by the second region and the third region,
(B-1) one source/drain region of the second transistor is constituted of the fourth region,
(B-2) the other source/drain region of the second transistor is constituted of the first region,
(B-3) a channel forming region of the second transistor is constituted of a surface region of the third region sandwiched by the first region and the fourth region,
(C) the diode is constituted of the third region and the fourth region,
(D) the gate portion is connected to a first memory-cell-selecting line,
(E) the second region is connected to a second memory-cell-selecting line, and
(F) the fourth region is connected to a write-in information setting line.

14 more elements

A semiconductor memory cell comprising a first transistor of a first conductivity type for read-out, a second transistor of a second conductivity type for write-in and a diode,

said semiconductor memory cell having;
(1) a first semi-conductive region of the first conductivity type,
(2) a second semi-conductive or conductive region forming a rectifier junction together with the first region,
(3) a third semi-conductive region of the second conductivity type, in contact with the first region and spaced from the second region,
(4) a fourth semi-conductive or conductive region formed in a surface region of the third region, said fourth region forming a rectifier junction together with the third region, and
(5) a gate portion shared by the first transistor and the second transistor, and formed on a barrier layer so as to bridge the second region and the third region and so as to bridge the first region and the fourth region,
wherein;
(A-1) one source,drain region of the first transistor is constituted of the fourth region,
(A-2) the other source/drain region of the first transistor is constituted of the first region,
(A-3) a channel forming region of the first transistor is constituted of a surface region of the third region sandwiched by the first region and the fourth region,
(B-1) one source/drain region of the second transistor is constituted of the second region,
(B-2) the other source/drain region of the second transistor is constituted of the third region,
(B-3) a channel forming region of the second transistor is constituted of a surface region of the first region sandwiched by the second region and the third region,
(C) the diode is constituted of the first region and the second region,
(D) the gate portion is connected to a first memory-cell-selecting line,
(E) the fourth region is connected to a second memory-cell-selecting line, and
(F) the second region is connected to a write-in information setting line.

14 more elements

A semiconductor memory cell provided with a semi-conductive layer having a first main surface and a second main surface opposed to the first main surface, said semiconductor memory cell comprising a first transistor of a first conductivity type for read-out, and a second transistor of a second conductivity type for write-in, and having;

(1) a first semi-conductive region of the first conductivity type, formed through the semi-conductive layer from the first main surface to the second main surface,
(2) a second semi-conductive region of the second conductivity type, formed through the semi-conductive layer from the first main surface to the second main surface and being in contact with the first region,
(3) a third semi-conductive or conductive region formed in a surface region, including the second main surface, of the first region and spaced from the second region, said third region forming a rectifier junction together with the first region,
(4) a fourth semi-conductive or conductive region formed in a surface region, including the first main surface, of the second region and spaced from the first region, said fourth region forming a rectifier junction together with the second region,
(5) a gate portion of the first transistor formed on a barrier layer formed on the first main surface so as to bridge the first region and the fourth region, and
(6) a gate portion of the second transistor formed on a barrier layer formed on the second main surface so as to bridge the second region and the third region,
wherein;
(A-1) one source/drain region of the first transistor is constituted of the fourth region,
(A-2) the other source/drain region of the first transistor is constituted of a surface region, including the first main surface, of the first region,
(A-3) a channel forming region of the first transistor is constituted of a surface region, including the first main surface, of the second region which surface region is sandwiched by the surface region, including the first main surface, of the first region and the fourth region,
(B-1) one source/drain region of the second transistor is constituted of the third region,
(B-2) the other source/drain region of the second transistor is constituted of a surface region, including the second main surface, of the second region,
(B-3) a channel forming region of the second transistor is constituted of a surface region, including the second main surface, of the first region which surface region is sandwiched by the third region and the surface region, including the second main surface, of the second region,
(C) the gate portion of the first transistor and the gate portion of the second transistor are connected to a first memory-cell-selecting line,
(D) the third region is connected to a write-in information setting line,
(E) the fourth region is connected to a second memory-cell-selecting line, and
(F) the other source/drain region of the first transistor is connected to a predetermined potential line.

14 more elements

A semiconductor memory cell provided with a semi-conductive layer having a first main surface and a second main surface opposed to the first main surface, said semiconductor memory cell comprising a first transistor of a first conductivity type for read-out, a second transistor of a second conductivity type for write-in and a diode, and having;

(1) a first semi-conductive region of the first conductivity type, formed through the semi-conductive layer from the first main surface to the second main surface,
(2) a second semi-conductive region of the second conductivity type, formed through the semi-conductive layer from the first main surface to the second main surface and being in contact with the first region,
(3) a third semi-conductive or conductive region formed in a surface region, including the second main surface, of the first region and spaced from the second region, said third region forming a rectifier junction together with the first region,
(4) a fourth semi-conductive or conductive region formed in a surface region, including the first main surface, of the second region and spaced from the first region, said fourth region forming a rectifier junction together with the second region,
(5) a gate portion of the first transistor formed on a barrier layer formed on the first main surface so as to bridge the first region and the fourth region, and
(6) a gate portion of the second transistor formed on a barrier layer formed on the second main surface so as to bridge the second region and the third region,
wherein;
(A-1) one source/drain region of the first transistor is constituted of the fourth region,
(A-2) the other source/drain region of the first transistor is constituted of a surface region, including the first main surface, of the first region,
(A-3) a channel forming region of the first transistor is constituted of a surface region, including the first main surface, of the second region which surface region is sandwiched by the surface region, including the first main surface, of the first region and the fourth region,
(B-1) one source/drain region of the second transistor is constituted of the third region,
(B-2) the other source/drain region of the second transistor is constituted of a surface region, including the second main surface, of the second region,
(B-3) a channel forming region of the second transistor is constituted of a surface region, including the second main surface, of the first region which surface region is sandwiched by the third region and the surface region, including the second main surface, of the second region,
(C) the diode is constituted of the first region and the third region,
(D) the gate portion of the first transistor and the gate portion of the second transistor are connected to a first memory-cell-selecting line,
(E) the third region is connected to a write-in information setting line, and
(F) the fourth region is connected to a second memory-cell-selecting line.

14 more elements

A semiconductor memory cell provided with a semi-conductive layer having a first main surface and a second main surface opposed to the first main surface, said semiconductor memory cell comprising a first semiconductor memory device and a second semiconductor memory device, said first semiconductor memory device comprising a first transistor of a first conductivity type for read-out and a first transistor of a second conductivity type for write-in, and said second semiconductor memory device comprising a second transistor of the first conductivity type for read-out and a second transistor of the second conductivity type for write-in,

said semiconductor memory cell having;
(1) a first semi-conductive region of the first conductivity type, formed through the semi-conductive layer from the first main surface to the second main surface,
(2-1) a second-A semi-conductive or conductive region formed in a surface region, including the first main surface, of the first region, said second-A region forming a rectifier junction together with the first region,
(2-2) a second-B semi-conductive or conductive region formed in a surface region, including the second main surface, of the first region, said second-B region forming a rectifier junction together with the first region
(3-1) a third-A semi-conductive region of the second conductivity type opposite to the first conductivity type, formed in a surface region, including the first main surface, of the first region and spaced from the second-A region,
(3-2) a third-B semi-conductive region of the second conductivity type opposite to the first conductivity type, formed in a surface region, including the second main surface, of the first region and spaced from the second-B region,
(4-1) a fourth-A semi-conductive or conductive region formed in a surface region, including the first main surface, of the third-A region, said fourth-A region forming a rectifier junction together with the third-A region,
(4-2) a fourth-B semi-conductive or conductive region formed in a surface region, including the second main surface, of the third-B region, said fourth-B region forming a rectifier junction together with the third-B region,
(5-1) a gate portion of the first semiconductor memory device formed on a first barrier layer formed on the first main surface so as to bridge the first region and the fourth-A region and so as to bridge the second-A region and the third-A region, and
(5-2) a gate portion of the second semiconductor memory device formed on a second barrier layer formed on the second main surface so as to bridge the first region and the fourth-B region and so as to bridge the second-B region and the third-B region,
wherein;
(A-1) one source/drain region of the first transistor for read-out is constituted of the fourth-A region,
(A-2) the other source/drain region of the first transistor for read-out is constituted of a surface region, including the first main surface, of the first region,
(A-3) a channel forming region of the first transistor for read-out is constituted of a surface region, including the first main surface, of the third-A region which surface region is sandwiched by the surface region, including the first main surface, of the first region and the fourth-A region,
(a-1) one source/drain region of the second transistor for read-out is constituted of the fourth-B region,
(a-2) the other source/drain region of the second transistor for read-out is constituted of a surface region, including the second main surface, of the first region,
(a-3) a channel forming region of the second transistor for read-out is constituted of a surface region, including the second main surface, of the third-B region which surface region is sandwiched by the surface region, including the second main surface, of the first region and the fourth-B region,
(B-1) one source/drain region of the first transistor for write-in is constituted of the second-A region,
(B-2) the other source/drain region of the first transistor for write-in is constituted of a surface region, including the first main surface, of the third-A region,
(B-3) a channel forming region of the first transistor for write-in is constituted of a surface region, including the first main surface, of the first region which surface region is sandwiched by the surface region, including the first main surface, of the third-A region and the second-A region,
(b-1) one source/drain region of the second transistor for write-in is constituted of the second-B region,
(b-2) the other source/drain region of the second transistor for write-in is constituted of a surface region, including the second main surface, of the third-B region,
(b-3) a channel forming region of the second transistor for write-in is constituted of a surface region, including the second main surface, of the first region which surface region is sandwiched by the surface region, including the second main surface, of the third-B region and the second-B region,
(C) the gate portion of the first semiconductor memory device is connected to a first-A memory-cell-selecting line,
(c) the gate portion of the second semiconductor memory device is connected to a first-B memory-cell-selecting line,
(D) the second-A region is connected to a write-in information setting line-A,
(d) the second-B region is connected to a write-in information setting line-B,
(E) the fourth-A region is connected to a second-A memory-cell-selecting line,
(e) the fourth-B region is connected to a second-B memory-cell-selecting line, and
(F) the first region is connected to a predetermined potential line.

27 more elements

A semiconductor memory cell provided with a semi-conductive layer having a first main surface and a second main surface opposed to the first main surface, said semiconductor memory cell comprising a first semiconductor memory device and a second semiconductor memory device, said first semiconductor memory device comprising a first transistor of a first conductivity type for read-out, a first transistor of a second conductivity type for write-in and a first diode, and said second semiconductor memory device comprising a second transistor of the first conductivity type for read-out, a second transistor of the second conductivity type for write-in and a second diode,

said semiconductor memory cell having;
(1) a first semi-conductive region of the first conductivity type, formed through the semi-conductive layer from the first main surface to the second main surface,
(2-1) a second-A semi-conductive or conductive region formed in a surface region, including the first main surface, of the first region, said second-A region forming a rectifier junction together with the first region,
(2-2) a second-B semi-conductive or conductive region formed in a surface region, including the second main surface, of the first region, said second-B region forming a rectifier junction together with the first region,
(3-1) a third-A semi-conductive region of the second conductivity type opposite to the first conductivity type, formed in a surface region, including the first main surface, of the first region and spaced from the second-A region,
(3-2) a third-B semi-conductive region of the second conductivity type opposite to the first conductivity type, formed in a surface region, including the second main surface, of the first region and spaced from the second-B region,
(4-1) a fourth-A semi-conductive or conductive region formed in a surface region, including the first main surface, of the third-A region, said fourth-A region forming a rectifier junction together with the third-A region,
(4-2) a fourth-B semi-conductive or conductive region formed in a surface region, including the second main surface, of the third-B region, said fourth-B region forming a rectifier junction together with the third-B region,
(5-1) a gate portion of the first semiconductor memory device formed on a first barrier layer formed on the first main surface so as to bridge the first region and the fourth-A region and so as to bridge the second-A region and the third-A region, and
(5-2) a gate portion of the second semiconductor memory device formed on a second barrier layer formed on the second main surface so as to bridge the first region and the fourth-B region and so as to bridge the second-B region and the third-B region,
wherein;
(A-1) one source/drain region of the first transistor for read-out is constituted of the fourth-A region,
(A-2) the other source/drain region of the first transistor for read-out is constituted of a surface region, including the first main surface, of the first region,
(A-3) a channel forming region of the first transistor for read-out is constituted of a surface region, including the first main surface, of the third-A region which surface region is sandwiched by the surface region, including the first main surface, of the first region and the fourth-A region,
(a-1) one source/drain region of the second transistor for read-out is constituted of the fourth-B region,
(a-2) the other source/drain region of the second transistor for read-out is constituted of a surface region, including the second main surface, of the first region,
(a-3) a channel forming region of the second transistor for read-out is constituted of a surface region, including the second main surface, of the third-B region which surface region is sandwiched by the surface region, including the second main surface, of the first region and the fourth-B region,
(B-1) one source/drain region of the first transistor for write-in is constituted of the second-A region,
(B-2) the other source/drain region of the first transistor for write-in is constituted of a surface region, including the first main surface, of the third-A region,
(B-3) a channel forming region of the first transistor for write-in is constituted of a surface region, including the first main surface, of the first region which surface region is sandwiched by the surface region, including the first main surface, of the third-A region and the second-A region,
(b-1) one source/drain region of the second transistor for write-in is constituted of the second-B region,
(b-2) the other source/drain region of the second transistor for write-in is constituted of a surface region, including the second main surface, of the third-B region,
(b-3) a channel forming region of the second transistor for write-in is constituted of a surface region, including the second main surface, of the first region which surface region is sandwiched by the surface region, including the second main surface, of the third-B region and the second-B region,
(C) the first diode is constituted of the first region and the second-A region,
(c) the second diode is constituted of the first region and the second-B region,
(D) the gate portion of the first semiconductor memory device is connected to a first-A memory-cell-selecting line,
(d) the gate portion of the second semiconductor memory device is connected to a first-B memory-cell-selecting line,
(E) the second-A region is connected to a write-in information setting line-A,
(e) the second-B region is connected to a write-in information setting line-B,
(F) the fourth-A region is connected to a second-A memory-cell-selecting line, and
(f) the fourth-B region is connected to a second-B memory-cell-selecting line.

28 more elements

A semiconductor memory cell provided with a semi-conductive layer having a first main surface and a second main surface opposed to the first main surface, said semiconductor memory cell comprising a first semiconductor memory device and a second semiconductor memory device, said first semiconductor memory device comprising a first transistor of a first conductivity type for read-out, a first transistor of a second conductivity type for write-in and a first diode, and said second semiconductor memory device comprising a second transistor of the first conductivity type for read-out, a second transistor of the second conductivity type for write-in and a second diode,

said semiconductor memory cell having;
(1) a first semi-conductive region of the first conductivity type, formed through the semi-conductive layer from the first main surface to the second main surface,
(2) a second semi-conductive region of the second conductivity type opposite to the first conductivity type, formed through the semi-conductive layer from the first main surface to the second main surface and being in contact with the first region,
(3-1) a third-A semi-conductive region of the second conductivity type, formed in a surface region, including the first main surface, of the first region and spaced from the second region,
(3-2) a third-B semi-conductive region of the second conductivity type, formed in a surface region, including the second main surface, of the first region and spaced from the second region,
(4-1) a fourth-A semi-conductive or conductive region formed in a surface region, including the first main surface, of the third-A region, said fourth-A region forming a rectifier junction together with the third-A region,
(4-2) a fourth-B semi-conductive or conductive region formed in a surface region, including the second main surface, of the third-B region, said fourth-B region forming a rectifier junction together with the third-B region,
(5-1) a gate portion of the first semiconductor memory device formed on a first barrier layer formed on the first main surface so as to bridge the first region and the fourth-A region and so as to bridge the second region and the third-A region, and
(5-2) a gate portion of the second semiconductor memory device formed on a second barrier layer formed on the second main surface so as to bridge the first region and the fourth-B region and so as to bridge the second region and the third-B region,
wherein;
(A-1) one source/drain region of the first transistor for read-out is constituted of the fourth-A region,
(A-2) the other source/drain region of the first transistor for read-out is constituted of a surface region, including the first main surface, of the first region,
(A-3) a channel forming region of the first transistor for read-out is constituted of a surface region, including the first main surface, of the third-A region which surface region is sandwiched by the surface region, including the first main surface, of the first region and the fourth-A region,
(a-1) one source/drain region of the second transistor for read-out is constituted of the fourth-B region,
(a-2) the other source/drain region of the second transistor for read-out is constituted of a surface region, including the second main surface, of the first region,
(a-3) a channel forming region of the second transistor for read-out is constituted of a surface region, including the second main surface, of the third-B region which surface region is sandwiched by the surface region, including the second main surface, of the first region and the fourth-B region,
(B-1) one source/drain region of the first transistor for write-in is constituted of a surface region, including the first main surface, of the second region,
(B-2) the other source/drain region of the first transistor for write-in is constituted of a surface region, including the first main surface, of the third-A region,
(B-3) a channel forming region of the first transistor for write-in is constituted of a surface region, including the first main surface, of the first region which surface region is sandwiched by the surface region, including the first main surface, of the second region and the surface region, including the first main surface, of the third-A region,
(b-1) one source/drain region of the second transistor for write-in is constituted of a surface region, including the second main surface, of the second region,
(b-2) the other source/drain region of the second transistor for write-in is constituted of a surface region, including the second main surface, of the third-B region,
(b-3) a channel forming region of the second transistor for write-in is constituted of a surface region, including the second main surface, of the first region which surface region is sandwiched by the surface region, including the second main surface, of the second region and the surface region, including the second main surface, of the third-B region,
(C) the first diode is in common with the second diode, and each of the first diode and the second diode is constituted of the first region and the second region,
(D) the gate portion of the first semiconductor memory device is connected to a first-A memory-cell-selecting line,
(d) the gate portion of the second semiconductor memory device is connected to a first-B memory-cell-selecting line,
(E) the second region is connected to a write-in information setting line,
(F) the fourth-A region is connected to a second-A memory-cell-selecting line, and
(f) the fourth-B region is connected to a second-B memory-cell-selecting line.

25 more elements

A semiconductor memory cell provided with a semi-conductive layer having a first main surface and a second main surface opposed to the first main surface, said semiconductor memory cell comprising a first semiconductor memory device and a second semiconductor memory device, said first semiconductor memory device comprising a first transistor of a first conductivity type for read-out, a first transistor of a second conductivity type for write-in and a first junction-field-effect transistor of the first conductivity type for current control, and said second semiconductor memory device comprising a second transistor of the first conductivity type for read-out, a second transistor of the second conductivity type for write-in and a second junction-field-effect transistor of the first conductivity type for current control,

said semiconductor memory cell having;
(1) a first semi-conductive region of the first conductivity type, formed through the semi-conductive layer from the first main surface to the second main surface,
(2-1) a second-A semi-conductive or conductive region formed in a surface region, including the first main surface, of the first region, said second-A region forming a rectifier junction together with the first region,
(2-2) a second-B semi-conductive or conductive region formed in a surface region, including the second main surface, of the first region, said second-B region forming a rectifier junction together with the first region,
(3-1) a third-A semi-conductive region of the second conductivity type opposite to the first conductivity type, formed in a surface region, including the first main surface, of the first region and spaced from the second-A region,
(3-2) a third-B semi-conductive region of the second conductivity type, formed in a surface region, including the second main surface, of the first region and spaced from the second-B region,
(4-1) a fourth-A semi-conductive or conductive region formed in a surface region, including the first main surface, of the third-A region, said fourth-A region forming a rectifier junction together with the third-A region,
(4-2) a fourth-B semi-conductive or conductive region formed in a surface region, including the second main surface, of the third-B region, said fourth-B region forming a rectifier junction together with the third-B region,
(5-1) a gate portion of the first semiconductor memory device formed on a first barrier layer formed on the first main surface so as to bridge the first region and the fourth-A region and so as to bridge the second-A region and the third-A region, and
(5-2) a gate portion of the second semiconductor memory device formed on a second barrier layer formed on the second main surface so as to bridge the first region and the fourth-B region and so as to bridge the second-B region and the third-B region,
wherein;
(A-1) one source/drain region of the first transistor for read-out is constituted of the fourth-A region,
(A-2) the other source/drain region of the first transistor for read-out is constituted of a surface region, including the first main surface, of the first region,
(A-3) a channel forming region of the first transistor for read-out is constituted of a surface region, including the first main surface, of the third-A region which surface region is sandwiched by the surface region, including the first main surface, of the first region and the fourth-A region,
(a-1) one source/drain region of the second transistor for read-out is constituted of the fourth-B region,
(a-2) the other source/drain region of the second transistor for read-out is constituted of a surface region, including the second main surface, of the first region,
(a-3) a channel forming region of the second transistor for read-out is constituted of a surface region, including the second main surface, of the third-B region which surface region is sandwiched by the surface region, including the second main surface, of the first region and the fourth-B region,
(B-1) one source/drain region of the first transistor for write-in is constituted of the second-A region,
(B-2) the other source/drain region of the first transistor for write-in is constituted of a surface region, including the first main surface, of the third-A region,
(B-3) a channel forming region of the first transistor for write-in is constituted of a surface region, including the first main surface, of the first region which surface region is sandwiched by the surface region, including the first main surface, of the third-A region and the second-A region,
(b-1) one source/drain region of the second transistor for write-in is constituted of the second-B region,
(b-2) the other source/drain region of the second transistor for write-in is constituted of a surface region, including the second main surface, of the third-B region,
(b-3) a channel forming region of the second transistor for write-in is constituted of a surface region, including the second main surface, of the first region which surface region is sandwiched by the surface region, including the second main surface, of the third-B region and the second-B region,
(C-1) gate regions of the first junction-field-effect transistor are constituted of the second-A region and the third-A region,
(C-2) a channel region of the first junction-field-effect transistor is constituted of a portion of the first region sandwiched by the second-A region and the third-A region,
(c-1) gate regions of the second junction-field-effect transistor are constituted of the second-B region and the third-B region,
(c-2) a channel region of the second junction-field-effect transistor is constituted of a portion of the first region sandwiched by the second-B region and the third-B region,
(D) the gate portion of the first semiconductor memory device is connected to a first-A memory-cell-selecting line,
(d) the gate portion of the second semiconductor memory device is connected to a first-B memory-cell-selecting line,
(E) the second-A region is connected to a write-in information setting line-A,
(e) the second-B region is connected to a write-in information setting line-B,
(F) the fourth-A region is connected to a second-A memory-cell-selecting line,
(f) the fourth-B region is connected to a second-B memory-cell-selecting line, and
(G) the first region is connected to a predetermined potential line.

31 more elements

A semiconductor memory cell provided with a semi-conductive layer having a first main surface and a second main surface opposed to the first main surface, said semiconductor memory cell comprising a first semiconductor memory device and a second semiconductor memory device, said first semiconductor memory device comprising a first transistor of a first conductivity type for read-out, a first transistor of a second conductivity type for write-in and a first junction-field-effect transistor of the first conductivity type for current control, and said second semiconductor memory device comprising a second transistor of the first conductivity type for read-out, a second transistor of the second conductivity type for write-in and a second junction-field-effect transistor of the first conductivity type for current control,

said semiconductor memory cell having;
(1) a first semi-conductive region of the first conductivity type, formed through the semi-conductive layer from the first main surface to the second main surface,
(2-1) a second-A semi-conductive or conductive region formed in a surface region, including the first main surface, of the first region, said second-A region forming a rectifier junction together with the first region,
(2-2) a second-B semi-conductive or conductive region formed in a surface region, including the second main surface, of the first region, said second-B region forming a rectifier junction together with the first region,
(3-1) a third-A semi-conductive region of the second conductivity type opposite to the first conductivity type, formed in a surface region, including the first main surface, of the first region and spaced from the second-A region,
(3-2) a third-B semi-conductive region of the second conductivity type, formed in a surface region, including the second main surface, of the first region and spaced from the second-B region,
(4-1) a fourth-A semi-conductive region of the first conductivity type, formed in a surface region, including the first main surface, of the third-A region,
(4-2) a fourth-B semi-conductive region of the first conductivity type, formed in a surface region, including the second main surface, of the third-B region,
(5-1) a fifth-A semi-conductive or conductive region formed in a surface region, including the first main surface, of the fourth-A region, said fifth-A region forming a rectifier junction together with the fourth-A region,
(5-2) a fifth-B semi-conductive or conductive region formed in a surface region, including the second main surface, of the fourth-B region, said fifth-B region forming a rectifier junction together with the fourth-B region,
(6-1) a gate portion of the first semiconductor memory device formed on a first barrier layer formed on the first main surface so as to bridge the first region and the fourth-A region and so as to bridge the second-A region and the third-A region, and
(6-2) a gate portion of the second semiconductor memory device formed on a second barrier layer formed on the second main surface so as to bridge the first region and the fourth-B region and so as to bridge the second-B region and the third-B region,
wherein;
(A-1) one source/drain region of the first transistor for read-out is constituted of the fourth-A region,
(A-2) the other source/drain region of the first transistor for read-out is constituted of a surface region, including the first main surface, of the first region,
(A-3) a channel forming region of the first transistor for read-out is constituted of a surface region, including the first main surface, of the third-A region which surface region is sandwiched by the surface region, including the first main surface, of the first region and the fourth-A region,
(a-1) one source/drain region of the second transistor for read-out is constituted of the fourth-B region,
(a-2) the other source/drain region of the second transistor for read-out is constituted of a surface region, including the second main surface, of the first region,
(a-3) a channel forming region of the second transistor for read-out is constituted of a surface region, including the second main surface, of the third-B region which surface region is sandwiched by the surface region, including the second main surface, of the first region and the fourth-B region,
(B-1) one source/drain region of the first transistor for write-in is constituted of the second-A region,
(B-2) the other source/drain region of the first transistor for write-in is constituted of a surface region, including the first main surface, of the third-A region,
(B-3) a channel forming region of the first transistor for write-in is constituted of a surface region, including the first main surface, of the first region which surface region is sandwiched by the surface region, including the first main surface, of the third-A region and the second-A region,
(b-1) one source/drain region of the second transistor for write-in is constituted of the second-B region,
(b-2) the other source/drain region of the second transistor for write-in is constituted of a surface region, including the second main surface, of the third-B region,
(b-3) a channel forming region of the second transistor for write-in is constituted of a surface region, including the second main surface, of the first region which surface region is sandwiched by the surface region, including the second main surface, of the third-B region and the second-B region,
(C-1) gate regions of the first junction-field-effect transistor are constituted of the fifth-A region and a portion of third-A region facing the fifth-A region,
(C-2) a channel region of the first junction-field-effect transistor is constituted of a portion of the fourth-A region sandwiched by the fifth-A region and said portion of the third-A region,
(C-3) source/drain regions of the first junction-field-effect transistor are constituted of portions of the fourth-A region, one of the portions of the fourth-A region extending from one end of the channel region of the first junction-field-effect transistor and the other of the portions of the fourth-A region extending from the other end of the channel region of the first junction-field-effect transistor,
(c-1) gate regions of the second junction-field-effect transistor are constituted of the fifth-B region and a portion of third-B region facing the fifth-B region,
(c-2) a channel region of the second junction-field-effect transistor is constituted of a portion of the fourth-B region sandwiched by the fifth-B region and said portion of the third-B region,
(c-3) source/drain regions of the second junction-field-effect transistor are constituted of portions of the fourth-B region, one of the portions of the fourth-B region extending from one end of the channel region of the second junction-field-effect transistor and the other of the portions of the fourth-B region extending from the other end of the channel region of the second junction-field-effect transistor,
(D) the gate portion of the first semiconductor memory device is connected to a first-A memory-cell-selecting line,
(d) the gate portion of the second semiconductor memory device is connected to a first-B memory-cell-selecting line,
(E) the second-A region is connected to a write-in information setting line-A,
(e) the second-B region is connected to a write-in information setting line-B,
(F) the fourth-A region is connected to a second-A memory-cell-selecting line,
(f) the fourth-B region is connected to a second-B memory-cell-selecting line,
(G) the first region is connected to a predetermined potential line,
(H) the fifth-A region is connected to the write-in information setting line-A, and
(h) the fifth-B region is connected to the write-in information setting line-B.

37 more elements

A semiconductor memory cell provided with a semi-conductive layer having a first main surface and a second main surface opposed to the first main surface, said semiconductor memory cell comprising a first semiconductor memory device and a second semiconductor memory device, said first semiconductor memory device comprising a first transistor of a first conductivity type for read-out, a first transistor of a second conductivity type for write-in, a first junction-field-effect transistor of the first conductivity type for current control and a third transistor of the second conductivity type for write-in, and said second semiconductor memory device comprising a second transistor of the first conductivity type for read-out, a second transistor of the second conductivity type for write-in, a second junction-field-effect transistor of the first conductivity type for current control and a fourth transistor of the second conductivity type for write-in,

said semiconductor memory cell having;
(1) a first semi-conductive region of the first conductivity type, formed through the semi-conductive layer from the first main surface to the second main surface,
(2-1) a second-A semi-conductive or conductive region formed in a surface region, including the first main surface, of the first region, said second-A region forming a rectifier junction together with the first region,
(2-2) a second-B semi-conductive or conductive region formed in a surface region, including the second main surface, of the first region, said second-B region forming a rectifier junction together with the first region,
(3-1) a third-A semi-conductive region of the second conductivity type opposite to the first conductivity type, formed in a surface region, including the first main surface, of the first region and spaced from the second-A region,
(3-2) a third-B semi-conductive region of the second conductivity type, formed in a surface region, including the second main surface, of the first region and spaced from the second-B region,
(4-1) a fourth-A semi-conductive region of the first conductivity type, formed in a surface region, including the first main surface, of the third-A region,
(4-2) a fourth-B semi-conductive region of the first conductivity type, formed in a surface region, including the second main surface, of the third-B region,
(5-1) a fifth-A semi-conductive or conductive region formed in a surface region, including the first main surface, of the fourth-A region, said fifth-A region forming a rectifier junction together with the fourth-A region,
(5-2) a fifth-B semi-conductive or conductive region formed in a surface region, including the second main surface, of the fourth-B region, said fifth-B region forming a rectifier junction together with the fourth-B region,
(6-1) a gate portion of the first semiconductor memory device formed on a first barrier layer formed on the first main surface so as to bridge the first region and the fourth-A region, so as to bridge the second-A region and the third-A region and so as to bridge the third-A region and the fifth-A region, and
(6-2) a gate portion of the second semiconductor memory device formed on a second barrier layer formed on the second main surface so as to bridge the first region and the fourth-B region, so as to bridge the second-B region and the third-B region and so as to bridge the third-B region and the fifth-b region,
wherein;
(A-1) one source/drain region of the first transistor for read-out is constituted of the fourth-A region,
(A-2) the other source/drain region of the first transistor for read-out is constituted of a surface region, including the first main surface, of the first region,
(A-3) a channel forming region of the first transistor for read-out is constituted of a surface region, including the first main surface, of the third-A region which surface region is sandwiched by the surface region, including the first main surface, of the first region and the fourth-A region,
(a-1) one source/drain region of the second transistor for read-out is constituted of the fourth-B region,
(a-2) the other source/drain region of the second transistor for read-out is constituted of a surface region, including the second main surface, of the first region,
(a-3) a channel forming region of the second transistor for read-out is constituted of a surface region, including the second main surface, of the third-B region which surface region is sandwiched by the surface region, including the second main surface, of the first region and the fourth-B region,
(B-1) one source/drain region of the first transistor for write-in is constituted of the second-A region,
(B-2) the other source/drain region of the first transistor for write-in is constituted of a surface region, including the first main surface, of the third-A region,
(B-3) a channel forming region of the first transistor for write-in is constituted of a surface region, including the first main surface, of the first region which surface region is sandwiched by the surface region, including the first main surface, of the third-A region and the second-A region,
(b-1) one source/drain region of the second transistor for write-in is constituted of the second-B region,
(b-2) the other source/drain region of the second transistor for write-in is constituted of a surface region, including the second main surface, of the third-B region,
(b-3) a channel forming region of the second transistor for write-in is constituted of a surface region, including the second main surface, of the first region which surface region is sandwiched by the surface region, including the second main surface, of the third-B region and the second-B region,
(C-1) gate regions of the first junction-field-effect transistor are constituted of the fifth-A region and a portion of third-A region facing the fifth-A region,
(C-2) a channel region of the first junction-field-effect transistor is constituted of a portion of the fourth-A region sandwiched by the fifth-A region and said portion of the third-A region,
(C-3) source/drain regions of the first junction-field-effect transistor are constituted of portions of the fourth-A region, one of the portions of the fourth-A region extending from one end of the channel region of the first junction-field-effect transistor and the other of the portions of the fourth-A region extending from the other end of the channel region of the first junction-field-effect transistor,
(c-1) gate regions of the second junction-field-effect transistor are constituted of the fifth-B region and a portion of third-B region facing the fifth-B region,
(c-2) a channel region of the second junction-field-effect transistor is constituted of a portion of the fourth-B region sandwiched by the fifth-B region and said portion of the third-B region,
(c-3) source/drain regions of the second junction-field-effect transistor are constituted of portions of the fourth-B region, one of the portions of the fourth-B region extending from one end of the channel region of the second junction-field-effect transistor and the other of the portions of the fourth-B region extending from the other end of the channel region of the second junction-field-effect transistor,
(D-1) one source/drain region of the third transistor for write-in is constituted of the surface region of the third-A region functioning as the channel forming region of the first transistor for read-out,
(D-2) the other source/drain region of the third transistor for write-in is constituted of the fifth-A region,
(D-3) a channel forming region of the third transistor for write-in is constituted of the surface region of the fourth-A region functioning as one source/drain region of the first transistor for read-out,
(d-1) one source/drain region of the fourth transistor for write-in is constituted of the surface region of the third-B region functioning as to the channel forming region of the second transistor for read-out,
(d-2) the other source/drain region of the fourth transistor for write-in is constituted of the fifth-B region,
(d-3) a channel forming region of the fourth transistor for write-in is constituted of the surface region of the fourth-B region functioning as one source/drain region of the second transistor for read-out,
(E) the gate portion of the first semiconductor memory device is connected to a first-A memory-cell-selecting line,
(e) the gate portion of the second semiconductor memory device is connected to a first-B memory-cell-selecting line,
(F) the second-A region is connected to a write-in information setting line-A,
(f) the second-B region is connected to a write-in information setting line-B,
(G) the fourth-A region is connected to a second-A memory-cell-selecting line,
(g) the fourth-B region is connected to a second-B memory-cell-selecting line, and
(H) the first region is connected to a predetermined potential line.

41 more elements

A semiconductor memory cell provided with a semi-conductive layer having a first main surface and a second main surface opposed to the first main surface, said semiconductor memory cell comprising a first semiconductor memory device and a second semiconductor memory device, said first semiconductor memory device comprising a first transistor of a first conductivity type for read-out, a first transistor of a second conductivity type for write-in, a first junction-field-effect transistor of the first conductivity type for current control and a first diode, and said second semiconductor memory device comprising a second transistor of the first conductivity type for read-out, a second transistor of the second conductivity type for write-in, a second junction-field-effect transistor of the first conductivity type for current control and a second diode,

said semiconductor memory cell having;
(1) a first semi-conductive region of the first conductivity type, formed through the semi-conductive layer from the first main surface to the second main surface,
(2-1) a second-A semi-conductive or conductive region formed in a surface region, including the first main surface, of the first region, said second-A region forming a rectifier junction together with the first region,
(2-2) a second-B semi-conductive or conductive region formed in a surface region, including the second main surface, of the first region, said second-B region forming a rectifier junction together with the first region,
(3-1) a third-A semi-conductive region of the second conductivity type opposite to the first conductivity type, formed in a surface region, including the first main surface, of the first region and spaced from the second-A region,
(3-2) a third-B semi-conductive region of the second conductivity type, formed in a surface region, including the second main surface, of the first region and spaced from the second-B region,
(4-1) a fourth-A semi-conductive region of the first conductivity type, formed in a surface region, including the first main surface, of the third-A region,
(4-2) a fourth-B semi-conductive region of the first conductivity type, formed in a surface region, including the second main surface, of the third-B region,
(5-1) a fifth-A semi-conductive or conductive region formed in a surface region, including the first main surface, of the fourth-A region, said fifth-A region forming a rectifier junction together with the fourth-A region,
(5-2) a fifth-B semi-conductive or conductive region formed in a surface region, including the second main surface, of the fourth-B region, said fifth-B region forming a rectifier junction together with the fourth-B region,
(6-1) a gate portion of the first semiconductor memory device formed on a first barrier layer formed on the first main surface so as to bridge the first region and the fourth-A region and so as to bridge the second-A region and the third-A region, and
(6-2) a gate portion of the second semiconductor memory device formed on a second barrier layer formed on the second main surface so as to bridge the first region and the fourth-B region and so as to bridge the second-B region and the third-B region,
wherein;
(A-1) one source/drain region of the first transistor for read-out is constituted of the fourth-A region,
(A-2) the other source/drain region of the first transistor for read-out is constituted of a surface region, including the first main surface, of the first region,
(A-3) a channel forming region of the first transistor for read-out is constituted of a surface region, including the first main surface, of the third-A region which surface region is sandwiched by the surface region, including the first main surface, of the first region and the fourth-A region,
(a-1) one source/drain region of the second transistor for read-out is constituted of the fourth-B region,
(a-2) the other source/drain region of the second transistor for read-out is constituted of a surface region, including the second main surface, of the first region,
(a-3) a channel forming region of the second transistor for read-out is constituted of a surface region, including the second main surface, of the third-B region which surface region is sandwiched by the surface region, including the second main surface, of the first region and the fourth-B region,
(B-1) one source/drain region of the first transistor for write-in is constituted of the second-A region,
(B-2) the other source/drain region of the first transistor for write-in is constituted of a surface region, including the first main surface, of the third-A region,
(B-3) a channel forming region of the first transistor for write-in is constituted of a surface region, including the first main surface, of the first region which surface region is sandwiched by the surface region, including the first main surface, of the third-A region and the second-A region,
(b-1) one source/drain region of the second transistor for write-in is constituted of the second-B region,
(b-2) the other source/drain region of the second transistor for write-in is constituted of a surface region, including the second main surface, of the third-B region,
(b-3) a channel forming region of the second transistor for write-in is constituted of a surface region, including the second main surface, of the first region which surface region is sandwiched by the surface region, including the second main surface, of the third-B region and the second-B region,
(C-1) gate regions of the first junction-field-effect transistor are constituted of the fifth-A region and a portion of third-A region facing the fifth-A region,
(C-2) a channel region of the first junction-field-effect transistor is constituted of a portion of the fourth-A region sandwiched by the fifth-A region and said portion of the third-A region,
(C-3) source,drain regions of the first junction-field-effect transistor are constituted of portions of the fourth-A region, one of the portions of the fourth-A region extending from one end of the channel region of the first junction-field-effect transistor and the other of the portions of the fourth-A region extending from the other end of the channel region of the first junction-field-effect transistor,
(c-1) gate regions of the second junction-field-effect transistor are constituted of the fifth-B region and a portion of third-B region facing the fifth-B region,
(c-2) a channel region of the second junction-field-effect transistor is constituted of a portion of the fourth-B region sandwiched by the fifth-B region and said portion of the third-B region,
(c-3) source/drain regions of the second junction-field-effect transistor are constituted of portions of the fourth-B region, one of the portions of the fourth-B region extending from one end of the channel region of the second junction-field-effect transistor and the other of the portions of the fourth-B region extending from the other end of the channel region of the second junction-field-effect transistor,
(D) the first diode is constituted of the second-A region and the first region,
(d) the second diode is constituted of the second-B region and the first region,
(E) the gate portion of the first semiconductor memory device is connected to a first-A memory-cell-selecting line,
(e) the gate portion of the second semiconductor memory device is connected to a first-B memory-cell-selecting line,
(F) the second-A region is connected to a write-in information setting line-A,
(f) the second-B region is connected to a write-in information setting line-B,
(G) the fourth-A region is connected to a second-A memory-cell-selecting line,
(g) the fourth-B region is connected to a second-B memory-cell-selecting line,
(H) the fifth-A region is connected to the write-in information setting line-A, and
(h) the fifth-B region is connected to the write-in information setting line-B.

38 more elements

A semiconductor memory cell provided with a semi-conductive layer having a first main surface and a second main surface opposed to the first main surface, said semiconductor memory cell comprising a first semiconductor memory device and a second semiconductor memory device, said first semiconductor memory device comprising a first transistor of a first conductivity type for read-out, a first transistor of a second conductivity type for write-in, a first junction-field-effect transistor of the first conductivity type for current control, a third transistor of the second conductivity type for write-in and a first diode, and said second semiconductor memory device comprising a second transistor of the first conductivity type for read-out, a second transistor of the second conductivity type for write-in, a second junction-field-effect transistor of the first conductivity type for current control, a fourth transistor of the second conductivity type for write-in and a second diode,

said semiconductor memory cell having;
(1) a first semi-conductive region of the first conductivity type, formed through the semi-conductive layer from the first main surface to the second main surface,
(2-1) a second-A semi-conductive or conductive region formed in a surface region, including the first main surfaces of the first region, said second-A region forming a rectifier junction together with the first region,
(2-2) a second-B semi-conductive or conductive region formed in a surface region, including the second main surface, of the first region, said second-B region forming a rectifier junction together with the first region,
(3-1) a third-A semi-conductive region of the second conductivity type opposite to the first conductivity type, formed in a surface region, including the first main surface, of the first region and spaced from the second-A region,
(3-2) a third-B semi-conductive region of the second conductivity type, formed in a surface region, including the second main surface, of the first region and spaced from the second-B region,
(4-1) a fourth-A semi-conductive region of the first conductivity type, formed in a surface region, including the first main surface, of the third-A region,
(4-2) a fourth-B semi-conductive region of the first conductivity type, formed in a surface region, including the second main surface, of the third-B region,
(5-1) a fifth-A semi-conductive or conductive region formed in a surface region, including the first main surface, of the fourth-A region, said fifth-A region forming a rectifier junction together with the fourth-A region,
(5-2) a fifth-B semi-conductive or conductive region formed in a surface region, including the second main surface, of the fourth-B region, said fifth-B region forming a rectifier junction together with the fourth-B region,
(6-1) a gate portion of the first semiconductor memory device formed on a first barrier layer formed on the first main surface so as to bridge the first region and the fourth-A region, so as to bridge the second-A region and the third-A region and so as to bridge the third-A region and the fifth-A region, and
(6-2) a gate portion of the second semiconductor memory device formed on a second barrier layer formed on the second main surface so as to bridge the first region and the fourth-B region, so as to bridge the second-B region and the third-B region and so as to bridge the third-B region and the fifth-b region,
wherein;
(A-1) one source/drain region of the first transistor for read-out is constituted of the fourth-A region,
(A-2) the other source/drain region of the first transistor for read-out is constituted of a surface region, including the first main surface, of the first region,
(A-3) a channel forming region of the first transistor for read-out is constituted of a surface region, including the first main surface, of the third-A region which surface region is sandwiched by the surface region, including the first main surface, of the first region and the fourth-A region,
(a-1) one source/drain region of the second transistor for read-out is constituted of the fourth-B region,
(a-2) the other source/drain region of the second transistor for read-out is constituted of a surface region, including the second main surface, of the first region,
(a-3) a channel forming region of the second transistor for read-out is constituted of a surface region, including the second main surface, of the third-B region which surface region is sandwiched by the surface region, including the second main surface, of the first region and the fourth-B region,
(B-1) one source/drain region of the first transistor for write-in is constituted of the second-A region,
(B-2) the other source/drain region of the first transistor for write-in is constituted of a surface region, including the first main surface, of the third-A region,
(B-3) a channel forming region of the first transistor for write-in is constituted of a surface region, including the first main surface, of the first region which surface region is sandwiched by the surface region, including the first main surface, of the third-A region and the second-A region,
(b-1) one source/drain region of the second transistor for write-in is constituted of the second-B region,
(b-2) the other source/drain region of the second transistor for write-in is constituted of a surface region, including the second main surface, of the third-B region,
(b-3) a channel forming region of the second transistor for write-in is constituted of a surface region, including the second main surface, of the first region which surface region is sandwiched by the surface region, including the second main surface, of the third-B region and the second-B region,
(C-1) gate regions of the first junction-field-effect transistor are constituted of the fifth-A region and a portion of third-A region facing the fifth-A region,
(C-2) a channel region of the first junction-field-effect transistor is constituted of a portion of the fourth-A region sandwiched by the fifth-A region and said portion of the third-A region,
(C-3) source/drain regions of the first junction-field-effect transistor are constituted of portions of the fourth-A region, one of the portions of the fourth-A region extending from one end of the channel region of the first junction-field-effect transistor and the other of the portions of the fourth-A region extending from the other end of the channel region of the first junction-field-effect transistor,
(c-1) gate regions of the second junction-field-effect transistor are constituted of the fifth-B region and a portion of third-B region facing the fifth-B region,
(c-2) a channel region of the second junction-field-effect transistor is constituted of a portion of the fourth-B region sandwiched by the fifth-B region and said portion of the third-B region,
(c-3) source/drain regions of the second junction-field-effect transistor are constituted of portions of the fourth-B region, one of the portions of the fourth-B region extending from one end of the channel region of the second junction-field-effect transistor and the other of the portions of the fourth-B region extending from the other end of the channel region of the second junction-field-effect transistor,
(D-1) one source/drain region of the third transistor for write-in is constituted of the surface region of the third-A region functioning as the channel forming region of the first transistor for read-out,
(D-2) the other source/drain region of the third transistor for write-in is constituted of the fifth-A region,
(D-3) a channel forming region of the third transistor for write-in is constituted of the surface region of the fourth-A region functioning as one source/drain region of the first transistor for read-out,
(d-1) one source/drain region of the fourth transistor for write-in is constituted of the surface region of the third-B region functioning as the channel forming region of the second transistor for read-out,
(d-2) the other source/drain region of the fourth transistor for write-in is constituted of the fifth-B region,
(d-3) a channel forming region of the fourth transistor for write-in is constituted of the surface region of the fourth-B region functioning as one source/drain region of the second transistor for read-out,
(E) the first diode is constituted of the second-A region and the first region,
(e) the second diode is constituted of the second-B region and the first region,
(F) the gate portion of the first semiconductor memory device is connected to a first-A memory-cell-selecting line,
(f) the gate portion of the second semiconductor memory device is connected to a first-B memory-cell-selecting line,
(G) the second-A region is connected to a write-in information setting line-A,
(g) the second-B region is connected to a write-in information setting line-B,
(H) the fourth-A region is connected to a second-A memory-cell-selecting line, and
(h) the fourth-B region is connected to a second-B memory-cell-selecting line.

42 more elements

A semiconductor memory cell provided with a semi-conductive layer having a first main surface and a second main surface opposed to the first main surface, said semiconductor memory cell comprising a first semiconductor memory device and a second semiconductor memory device, said first semiconductor memory device comprising a first transistor of a first conductivity type for read-out, a first transistor of a second conductivity type for write-in, a first junction-field-effect transistor of the first conductivity type for current control and a first diode, and said second semiconductor memory device comprising a second transistor of the first conductivity type for read-out, a second transistor of the second conductivity type for write-in, a second junction-field-effect transistor of the first conductivity type for current control and a second diode,

said semiconductor memory cell having;
(1) a first semi-conductive region of the first conductivity type, formed through the semi-conductive layer from the first main surface to the second main surface,
(2) a second semi-conductive region of the second conductivity type opposite to the first conductivity type, formed through the semi-conductive layer from the first main surface to the second main surface and being in contact with the first region,
(3-1) a third-A semi-conductive region of the second conductivity type, formed in a surface region, including the first main surface, of the first region and spaced from the second region,
(3-2) a third-B semi-conductive region of the second conductivity type, formed in a surface region, including the second main surface, of the first region and spaced from the second region,
(4-1) a fourth-A semi-conductive region of the first conductivity type, formed in a surface region, including the first main surface, of the third-A region,
(4-2) a fourth-B semi-conductive region of the first conductivity type, formed in a surface region, including the second main surface, of the third-B region,
(5-1) a fifth-A semi-conductive or conductive region formed in a surface region, including the first main surface, of the fourth-A region, said fifth-A region forming a rectifier junction together with the fourth-A region,
(5-2) a fifth-B semi-conductive or conductive region formed in a surface region, including the second main surface, of the fourth-B region, said fifth-B region forming a rectifier junction together with the fourth-B region,
(6-1) a gate portion of the first semiconductor memory device formed on a first barrier layer formed on the first main surface so as to bridge the first region and the fourth-A region and so as to bridge the second region and the third-A region, and
(6-2) a gate portion of the second semiconductor memory device formed on a second barrier layer formed on the second main surface so as to bridge the first region and the fourth-B region and so as to bridge the second region and the third-B region,
wherein;
(A-1) one source/drain region of the first transistor for read-out is constituted of the fourth-A region,
(A-2) the other source/drain region of the first transistor for read-out is constituted of a surface region, including the first main surface, of the first region,
(A-3) a channel forming region of the first transistor for read-out is constituted of a surface region, including the first main surface, of the third-A region which surface region is sandwiched by the surface region, including the first main surface, of the first region and the fourth-A region,
(a-1) one source/drain region of the second transistor for read-out is constituted of the fourth-B region,
(a-2) the other source/drain region of the second transistor for read-out is constituted of a surface region, including the second main surface, of the first region,
(a-3) a channel forming region of the second transistor for read-out is constituted of a surface region, including the second main surface, of the third-B region which surface region is sandwiched by the surface region, including the second main surface, of the first region and the fourth-B region,
(B-1) one source/drain region of the first transistor for write-in is constituted of a surface region, including the first main surface, of the second region,
(B-2) the other source/drain region of the first transistor for write-in is constituted of a surface region, including the first main surface, of the third-A region,
(B-3) a channel forming region of the first transistor for write-in is constituted of a surface region, including the first main surface, of the first region which surface region is sandwiched by the surface region, including the first main surface, of the third-A region and the surface region, including the first main surface, of the second region,
(b-1) one source/drain region of the second transistor for write-in is constituted of a surface region, including the second main surface, of the second region,
(b-2) the other source/drain region of the second transistor for write-in is constituted of a surface region, including the second main surface, of the third-B region,
(b-3) a channel forming region of the second transistor for write-in is constituted of a surface region, including the second main surface, of the first region which surface region is sandwiched by the surface region, including the second main surface, of the third-B region and the surface region, including the second main surface, of the second region,
(C-1) gate regions of the first junction-field-effect transistor are constituted of the fifth-A region and a portion of third-A region facing the fifth-A region,
(C-2) a channel region of the first junction-field-effect transistor is constituted of a portion of the fourth-A region sandwiched by the fifth-A region and said portion of the third-A region,
(C-3) source/drain regions of the first junction-field-effect transistor are constituted of portions of the fourth-A region, one of the portions of the fourth-A region extending from one end of the channel region of the first junction-field-effect transistor and the other of the portions of the fourth-A region extending from the other end of the channel region of the first junction-field-effect transistor,
(c-1) gate regions of the second junction-field-effect transistor are constituted of the fifth-B region and a portion of third-B region facing the fifth-B region,
(c-2) a channel region of the second junction-field-effect transistor is constituted of a portion of the fourth-B region sandwiched by the fifth-B region and said portion of the third-B region,
(c-3) source/drain regions of the second junction-field-effect transistor are constituted of portions of the fourth-B region, one of the portions of the fourth-B region extending from one end of the channel region of the second junction-field-effect transistor and the other of the portions of the fourth-B region extending from the other end of the channel region of the second junction-field-effect transistor,
(D) each of the first diode and the second diode is constituted of the second region and the first region,
(E) the gate portion of the first semiconductor memory device is connected to a first-A memory-cell-selecting line,
(e) the gate portion of the second semiconductor memory device is connected to a first-B memory-cell-selecting line,
(F) the second region is connected to a write-in information setting line,
(G) the fourth-A region is connected to a second-A memory-cell-selecting line,
(g) the fourth-B region is connected to a second-B memory-cell-selecting line, and
(H) the fifth-A region and the fifth-B region are connected to the write-in information setting line.

34 more elements

A semiconductor memory cell provided with a semi-conductive layer having a first main surface and a second main surface opposed to the first main surface, said semiconductor memory cell comprising a first semiconductor memory device and a second semiconductor memory device, said first semiconductor memory device comprising a first transistor of a first conductivity type for read-out, a first transistor of a second conductivity type for write-in, a first junction-field-effect transistor of the first conductivity type for current control, a third transistor of the second conductivity type for write-in and a first diode, and said second semiconductor memory device comprising a second transistor of the first conductivity type for read-out, a second transistor of the second conductivity type for write-in, a second junction-field-effect transistor of the first conductivity type for current control, a fourth transistor of the second conductivity type for write-in and a second diode,

said semiconductor memory cell having;
(1) a first semi-conductive region of the first conductivity type, formed through the semi-conductive layer from the first main surface to the second main surface,
(2) a second semi-conductive region of the second conductivity type opposite to the first conductivity type, formed through the semi-conductive layer from the first main surface to the second main surface and being in contact with the first region,
(3-1) a third-A semi-conductive region of the second conductivity type, formed in a surface region, including the first main surface, of the first region and spaced from the second region,
(3-2) a third-B semi-conductive region of the second conductivity type, formed in a surface region, including the second main surface, of the first region and spaced from the second region,
(4-1) a fourth-A semi-conductive region of the first conductivity type, formed in a surface region, including the first main surface, of the third-A region,
(4-2) a fourth-B semi-conductive region of the first conductivity type, formed in a surface region, including the second main surface, of the third-B region,
(5-1) a fifth-A semi-conductive or conductive region formed in a surface region, including the first main surface, of the fourth-A region, said fifth-A region forming a rectifier junction together with the fourth-A region,
(5-2) a fifth-B semi-conductive or conductive region formed in a surface region, including the second main surface, of the fourth-B region, said fifth-B region forming a rectifier junction together with the fourth-B region,
(6-1) a gate portion of the first semiconductor memory device formed on a first barrier layer formed on the first main surface so as to bridge the first region and the fourth-A region, so as to bridge the second region and the third-A region and so as to bridge the third-A region and the fifth-A region, and
(6-2) a gate portion of the second semiconductor memory device formed on a second barrier layer formed on the second main surface so as to bridge the first region and the fourth-B region, so as to bridge the second region and the third-B region and so as to bridge the third-B region and the fifth-b region,
wherein;
(A-1) one source/drain region of the first transistor for read-out is constituted of the fourth-A region,
(A-2) the other source/drain region of the first transistor for read-out is constituted of a surface region, including the first main surface, of the first region,
(A-3) a channel forming region of the first transistor for read-out is constituted of a surface region, including the first main surface, of the third-A region which surface region is sandwiched by the surface region, including the first main surface, of the first region and the fourth-A region,
(a-1) one source/drain region of the second transistor for read-out is constituted of the fourth-B region,
(a-2) the other source/drain region of the second transistor for read-out is constituted of a surface region, including the second main surface, of the first region,
(a-3) a channel forming region of the second transistor for read-out is constituted of a surface region, including the second main surface, of the third-B region which surface region is sandwiched by the surface region, including the second main surface, of the first region and the fourth-B region,
(B-1) one source/drain region of the first transistor for write-in is constituted of a surface region, including the first main surface, of the second region,
(B-2) the other source/drain region of the first transistor for write-in is constituted of a surface region, including the first main surface, of the third-A region,
(B-3) a channel forming region of the first transistor for write-in is constituted of a surface region, including the first main surface, of the first region which surface region is sandwiched by the surface region, including the first main surface, of the third-A region and the surface region, including the first main surface, of the second region,
(b-1) one source/drain region of the second transistor for write-in is constituted of a surface region, including the second main surface, of the second region,
(b-2) the other source/drain region of the second transistor for write-in is constituted of a surface region, including the second main surface, of the third-B region,
(b-3) a channel forming region of the second transistor for write-in is constituted of a surface region, including the second main surface, of the first region which surface region is sandwiched by the surface region, including the second main surface, of the third-B region and the surface region, including the second main surface, of the second region,
(C-1) gate regions of the first junction-field-effect transistor are constituted of the fifth-A region and a portion of third-A region facing the fifth-A region,
(C-2) a channel region of the first junction-field-effect transistor is constituted of a portion of the fourth-A region sandwiched by the fifth-A region and said portion of the third-A region,
(C-3) source/drain regions of the first junction-field-effect transistor are constituted of portions of the fourth-A region, one of the portions of the fourth-A region extending from one end of the channel region of the first junction-field-effect transistor and the other of the portions of the fourth-A region extending from the other end of the channel region of the first junction-field-effect transistor,
(c-1) gate regions of the second junction-field-effect transistor are constituted of the fifth-B region and a portion of third-B region facing the fifth-B region,
(c-2) a channel region of the second junction-field-effect transistor is constituted of a portion of the fourth-B region sandwiched by the fifth-B region and said portion of the third-B region,
(c-3) source/drain regions of the second junction-field-effect transistor are constituted of portions of the fourth-B region, one of the portions of the fourth-B region extending from one end of the channel region of the second junction-field-effect transistor and the other of the portions of the fourth-B region extending from the other end of the channel region of the second junction-field-effect transistor,
(D-1) one source/drain region of the third transistor for write-in is constituted of the surface region of the third-A region functioning as the channel forming region of the first transistor for read-out,
(D-2) the other source/drain region of the third transistor for write-in is constituted of the fifth-A region,
(D-3) a channel forming region of the third transistor for write-in is constituted of the surface region of the fourth-A region functioning as one source/drain region of the first transistor for read-out,
(d-1) one source/drain region of the fourth transistor for write-in is constituted of the surface region of the third-B region functioning as the channel forming region of the second transistor for read-out,
(d-2) the other source/drain region of the fourth transistor for write-in is constituted of the fifth-B region,
(d-3) a channel forming region of the fourth transistor for write-in is constituted of the surface region of the fourth-B region functioning as one source/drain region of the second transistor for read-out,
(E) each of the first diode and the second diode is constituted of the second region and the first region,
(F) the gate portion of the first semiconductor memory device is connected to a first-A memory-cell-selecting line,
(f) the gate portion of the second semiconductor memory device is connected to a first-B memory-cell-selecting line,
(G) the second region is connected to a write-in information-setting line,
(H) the fourth-A region is connected to a second-A memory-cell-selecting line, and
(h) the fourth-B region is connected to a second-B memory-cell-selecting line.

39 more elements

Semiconductor memory cell and method of manufacturing the same

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Semiconductor memory cell and method of manufacturing the same

Life of this patent

Abstract

Claims133