ESD protection circuit for SOI technology
AssigneeWinbond Electronics Corp.
InventorTa-Lee Yu
Life of this patent
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Abstract
An ESD protection circuit is fabricated on a semiconductor block on an insulating layer overlying a supporting substrate. The ESD protection circuit comprises a first N-type doped region, a first P-type doped region, a second N-type doped region and a second P-type doped region sequentially formed in the semiconductor block, and a stacked structure overlying the first P-type doped region and the second N-type doped region, wherein the first N-type doped region is more heavily doped than the second N-type doped region and the first P-type doped region is more lightly doped than the second P-type doped region.
Claims19
An ESD protection circuit fabricated on a semiconductor block on an insulating layer overlying a supporting substrate, said ESD protection circuit comprising:
- a first N-type doped region, a first P-type doped region, a second N-type doped region and a second P-type doped region sequentially formed in said semiconductor block, where said first N-type doped region is more heavily doped than said second N-type doped region and first P-type doped region is more lightly doped than said second p-type doped region;
- and
- a stacked structure including a dielectric layer and a conductive layer sequentially overlying said first P-type doped region and said second N-type doped region;
- wherein said first N-type doped region and said second P-type doped region are respectively coupled to a relatively low voltage and a relatively high voltage during operation.
An ESD protection circuit fabricate on a semiconductor layer of an SOI structure, comprising:
- a semiconductor-controlled rectifier comprising a first N-type doped layer, a first P-type doped layer, a second N-type doped layer and a second P-type doped layer sequentially formed in said semiconductor layer, said first P-type doped layer acting as a cathode gate and said second N-type doped layer acting as an anode gate;
- and
- a gate structure including a dielectric layer and a conductive layer sequentially overlying said cathode gate and said anode gate of said semiconductor-controlled rectifier;
- wherein said first N-type doped region and said second P-type doped region are respectively coupled to a relatively low voltage and a relatively high voltage during operation.
Dependencies are inferred from the claim text.