Guard ring structure with deep N well on ESD devices
AssigneeEtron Technology, Inc.
InventorsKun-Zen Chang, Deng-Shun Chang, Rong-Tai Kao
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Abstract
In this invention a deep N-type wall is created surrounding an area that contains an ESD device, or circuit. The ESD device, or circuit, is connected to a chip pad and is first surrounded by a P+ guard ring. The P+ guard ring is then surrounded by the deep N-type wall to block excess current from an ESD event or voltage overshoot from reaching the internal circuitry. The deep N-type wall comprises an N+ diffusion within an N-well which is on top of a deep N-well. The height of the deep N-type wall is approximately 4 to 6 micrometers which provides a capability to absorb much of the current from an ESD event or voltage overshoot.
Claims16
An ESD (electrostatic discharge) device with protective guard rings, comprising:
- a) an ESD device on a P-substrate connected to a chip pad on surface of said P-substrate,
- b) said ESD device surrounded by and laterally separated from a P+ diffusion guard ring within said P-substrate, wherein said P+ diffusion guard ring starts at the surface of the P-substrate and extends vertically a first distance within the P-substrate,
- c) an N+ diffusion guard ring surrounding and laterally separated from said P+ diffusion guard ring,
- d) said N+ diffusion guard ring contained within an N-well surrounding and laterally separated from the region of said P+ diffusion guard ring, wherein said N+ diffusion guard ring starts at the surface of the P-substrate and extends vertically a second distance within the P-substrate,
- e) said N-well sifting on top of a deep N-well surrounding and laterally separated from said P+ diffusion guard ring on said P-substrate, wherein said deep N-well starts at said second distance within said P-substrate and extends vertically to a third distance further from the surface of said substrate than said second distance.
A method of creating an ESD protection for integrated circuit chips, comprising:
- a) forming a deep N-well on a P-substrate surrounding an area to contain an ESD device, wherein said deep N-well starts at a first distance below a surface of said P-substrate and extends vertically a second distance further from said surface,
- b) forming an N-well on top of the deep N-well extending vertically from the surface of the P-substrate to said first distance and said deep N-well, and surrounding said area containing said ESD device,
- c) forming a P-well separated from and contained within an area enclosed by said N-well and surrounding said area containing said ESD device,
- d) forming an N+ diffusion within said N-well and surrounding said area containing said P-well and said ESD device,
- e) forming a P+ diffusion within said P-well separated from and within inner boundaries of said N-well and surrounding said area containing said ESD device,
- f) forming said ESD device enclosed by said P+ diffusion contained within said P-well, wherein said P-well is separated from and further enclosed by said N-well.
Dependencies are inferred from the claim text.