Semiconductor device having input-output protection circuit

A semiconductor device comprising:

• a SOI substrate:
• an input-output protecting circuit section connected to a signal terminal, configured to protect an internal circuit and formed on said SOI substrate;
• and
• a potential fixing node which is one of a power supply node and a reference potential node
• said input-output protecting circuit section including:
• a MOS transistor of a predetermined conductivity type having a first electrode region connected to said signal terminal and a second electrode region connected to said potential fixing node;
• a first capacitor inserted between said first electrode region and a gate electrode of said MOS transistor;
• a second capacitor inserted between said potential fixing node and said gate electrode of said MOS transistor;
• and
• a pseudo MOS transistor section comprising a pseudo gate electrode, a pseudo gate insulation film, and first, second and third diffusing regions corresponding to said gate electrode of said MOS transistor, a gate insulation film, a channel formation region, said first electrode region and said second electrode region respectively, and does not function as a transistor,
• wherein said first capacitor includes a capacitor formed by a part of said gate electrode of said MOS transistor and a part of said first electrode region with said gate insulation film interposed therebetween,
• wherein said second capacitor includes a capacitor formed between said pseudo gate electrode and said channel formation region of said pseudo MOS transistor, and
• wherein a capacity value of said second capacitor is set greater than that of said first capacitor in such a manner that said MOS transistor is reversely biased when said normal operation signal is applied to said signal terminal, and is forward biased when a surge voltage having a first or second polarity is applied to said signal terminal.

A semiconductor device comprising:

• an SOI substrate;
• an input-output protecting circuit section comprising a MOS transistor for input-output protection formed on said SOI substrate;
• and
• an internal circuit section comprising a MOS transistor for an internal circuit formed on said SOI substrate and configured to perform a predetermined signal processing;
• wherein said MOS transistor for input-output protection has a structure in which punch through is caused more easily than in said MOS transistor for an internal circuit.

A semiconductor device comprising an input-output protecting circuit section formed on a SOI substrate and having first and second diodes connected to a signal terminal,

• said input-output protecting circuit section including:
• a first semiconductor region of a first conductivity type;
• a second semiconductor region of a second conductivity type formed adjacently to said first semiconductor region;
• a third semiconductor region of the first conductivity type formed independent of said first and second semiconductor regions;
• a fourth semiconductor region of the second conductivity type formed adjacently to said third semiconductor region;
• first to fourth silicide regions which are selectively formed on surfaces of said first to fourth semiconductor regions, respectively;
• an interlayer dielectric film formed by covering said first to fourth semiconductor regions including said first to fourth silicide regions, said interlayer dielectric film having first and fourth openings formed on said first to fourth silicide regions, respectively;
• a first wiring layer connected to a reference potential and formed on said first silicide region through said first opening of said interlayer dielectric film;
• a second wiring layer connected to said signal terminal and formed on said second and third silicide regions through said first and second openings of said interlayer dielectric film;
• and
• a third wiring layer connected to a power supply and formed on said fourth silicide region through said fourth opening of said interlayer dielectric film,
• wherein said first diode is formed by said first and second semiconductor regions, and said second diode is formed by said third and fourth semiconductor regions.