US 6,274,411 B1Granted

Method for manufacturing electronic devices, comprising non-salicided non-volatile memory cells, non-salicided HV transistors, and LV transistors with salicided junctions with few masks

AssigneeSTMicroelectronics S.r.l.

InventorsMatteo Patelmo, Bruno Vajana, Giovanna Dalla Libera, Carlo Cremonesi, Nadia Galbiati

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Abstract

A method of forming source and drain regions for LV transistors that includes the steps of forming sacrificial spacers laterally to LV gate regions; forming LV source and drain regions in a self-aligned manner with the sacrificial spacers; removing the sacrificial spacers; forming HV gate regions of HV transistors; forming gate regions of selection transistors; forming control gate regions of memory transistors; simultaneously forming LDD regions self-aligned with the LV gate regions, HV source and drain regions self-aligned with the HV gate regions, source and drain regions self-aligned with the selection gate region and floating gate region; depositing a dielectric layer; covering the HV and memory areas with a protection silicide mask; anisotropically etching the dielectric layer, to form permanent spacers laterally to the LV gate regions; removing the protection silicide mask; and forming silicide regions on the LV source and drain regions and on the LV gate regions.

Claims19

Dependent claims

A method for manufacturing electronic devices having LV transistors, HV transistors and memory cells, the method comprising:

a) forming LV gate oxide regions above first areas of a silicon substrate where low-voltage transistors are to be formed, HV oxide regions above second areas of said substrate where high-voltage transistors are to be formed, selection oxide regions, tunnel oxide regions, and matrix oxide regions, above third areas of said substrate where selection transistors and memory transistors of EEPROM cells are to be formed;
b) forming floating gate regions above said tunnel oxide regions and said matrix oxide regions;
c) forming insulating regions above said floating gate regions;
d) forming LV gate regions above said LV gate oxide regions;
e) forming first source and drain regions laterally to said LV gate regions;
f) forming silicide regions on said LV source and drain regions and on said LV gate regions;
g) forming semiconductor material regions completely covering said second and third areas;
and
h) forming HV gate regions above said HV oxide regions, selection gate regions above said selection oxide regions, and control gate regions above said insulating regions, wherein said step e) of forming first source and drain regions laterally to said LV gate regions comprises:
i) forming sacrificial spacers laterally to said LV gate regions;
j) forming LV source and drain regions in said first areas, in a self-aligned manner with said sacrificial spacers, said LV source and drain regions having a first doping level;
k) removing said sacrificial spacers;
and
l) doping the LV gate oxide regions to form LDD regions laterally to said LV gate regions, inside said first areas, in a self-aligned manner with said LV gate regions, and said LDD regions having a second doping level lower than said first doping level.

11 more elements

Dependencies are inferred from the claim text.