Method to preserve the testing chip for package's quality
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWen-Cheng Chien, Ho-Yin Yiu, Hui-Chen Chu
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Abstract
A method for eliminating metal line corrosion for semiconductor packages where exposed metal lines are exposed to the atmosphere for an extended period of time. A passivation layer is deposited over the active die of the semiconductor package, a layer of polymer film is deposited over the passivation layer and over the exposed conducting lines. At the time that the semiconductor package must be tested, including testing for corrosion of the exposed metal lines, the polymer layer is removed and the molding compound is applied. The semiconductor package is now tested. The added step of depositing a layer of polymer film has protected the interconnecting conducting lines from corrosion.
Claims37
A method for protecting exposed conducting lines within an integrated circuit package, comprising:
- a printed circuit board having upper and lower opposed surfaces, the lower surface having a plurality of solderable pads;
- one or more semiconductor devices electrically and mechanically connected to the upper surface of the printed circuit board, said printed circuit board having exposed areas and electrically connected to the plurality of pads via the circuit board;
- a plasma enhanced (PE) layer of oxide deposited over said semiconductor devices further deposited over the exposed areas of said printed circuit board;
- a plurality of dielectric depositions said depositions deposited and etched over said layer of PE oxide and positioned above and aligned with said semiconductor devices;
- a plurality of interconnecting conducting lines deposited over said layer of PE oxide and having spaces therebetween and positioned at a location that is not in the immediate vicinity of said semiconductor devices and is not aligned with said semiconductor devices;
- a passivation layer deposited over said plurality of dielectric depositions further partially deposited over said PE oxide layer where this layer is in the immediate vicinity of said semiconductor devices;
- and
- a polymer layer deposited over said passivation layer further deposited over said plurality of interconnecting conducting lines and the spaces therebetween.
A method for protecting and testing semiconductor packages, consisting of:
- manufacturing said semiconductor package;
- depositing a passivation layer over the circuit elements of said semiconductor package said passivation layer not to cover exposed conducting lines within said semiconductor package;
- depositing a layer of polymer film over said passivation layer further including exposed conducting lines within said semiconductor package;
- removing said polymer film;
- testing said semiconductor package for line corrosion;
- depositing a layer of molding compound;
- and
- testing said semiconductor package for line corrosion.
Dependencies are inferred from the claim text.